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7–24
Chapter 7: Functional Description—High-Performance Controller II
Register Maps Description
Table 7–17. Address 0x123 Memory Timing Parameters Register 0
Bit
Name
Default
Access
Description
3:0
tRCD
—
RW
The activate to read or write a timing parameter.
The range of legal values is 2-11 cycles.
7:4
tRRD
—
RW
The activate to activate a timing parameter. The
range of legal values is 2-8 cycles.
11:8
tRP
—
RW
The precharge to activate a timing parameter. The
range of legal values is 2-11 cycles.
15:12
tMRD
—
RW
The mode register load time parameter. This
value is not used by the controller, as the
controller derives the correct value from the
memory type setting.
23:16
tRAS
—
RW
The activate to precharge a timing parameter. The
range of legal values is 4-29 cycles.
31:24
tRC
—
RW
The activate to activate a timing parameter. The
range of legal values is 8-40 cycles.
Table 7–18. Address 0x124 Memory Timing Parameters Register 1
Bit
Name
Default
Access
Description
3:0
tWTR
—
RW
The write to read a timing parameter. The range
of legal values is 1-10 cycles.
7:4
tRTP
—
RW
The read to precharge a timing parameter. The
range of legal values is 2-8 cycles.
15:8
tFAW
—
RW
The four-activate window timing parameter. The
range of legal values is 6-32 cycles.
31:16
Reserved
0
—
Reserved for future use.
Table 7–19. Address 0x125 Memory Timing Parameters Register 2
Bit
Name
Default
Access
Description
15:0
tREFI
—
RW
The refresh interval timing parameter. The range
of legal values is 780-6240 cycles.
23:16
tRFC
—
RW
The refresh cycle timing parameter. The range of
legal values is 12-88 cycles.
31:24
Reserved
0
—
Reserved for future use.
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
December 2010 Altera Corporation