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Simulation Parameters and Code Generation
Sample Time Propagation
Inherited sample times in source blocks (e.g., a root inport) can sometimes lead
to unexpected and unintended sample time assignments. Since a block may
specify an inherited sample time, information available at the outset is often
insufficient to compile a block diagram completely. In such cases, the Simulink
engine propagates the known or assigned sample times to those blocks that
have inherited sample times but which have not yet been assigned a sample
time. Thus, Simulink continues to fill in the blanks (the unknown sample
times) until sample times have been assigned to as many blocks as possible.
Blocks that still do not have a sample time are assigned a default sample time
according to the following rules:
1 If the current system has at least one rate in it, the block is assigned the
fastest rate.
2 If no rate exists and the model is configured for a variable-step solver, the
block is assigned a continuous sample time (but fixed in minor time steps).
Note that the Real-Time Workshop (with the exception of the S-Function
Target) does not currently support variable-step solvers.
3 If no rate exists and the model is configured for a fixed-step solver, the block
is assigned a discrete sample time of (Tf - Ti)/50, where Ti is the simulation
start time and Tf is the simulation stop time. If Tf is infinity, the default
sample time is set to 0.2.
To ensure a completely deterministic model (one where no sample times are set
using the above rules), you should explicitly specify the sample time of all your
source blocks. Source blocks include root inport blocks and any blocks without
input ports. You do not have to set subsystem input port sample times. You
may want to do so, however, when creating modular systems.
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