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Chapter 12: Stratix V Transceiver Native PHY IP Core
10G PCS Parameters
12–23
Table 12–21. 10G RX FIFO Parameters (Part 2 of 3)
Parameter
Enable RX FIFO deskew
(interlaken)
Enable RX FIFO alignment word
deletion (interlaken)
Enable RX FIFO control word
deletion (interlaken)
Range
Description
On/Off
When you turn this option On, the RX FIFO also performs deskew.
This option is only available for the Interlaken protocol.
On/Off
When you turn this option On, all alignment words (sync words),
including the first sync word, are removed after frame
synchronization is achieved. If you enable this option, you must
also enable control word deletion.
On/Off
When you turn this option On, the rx_control_del parameter
enables or disables writing the Interlaken control word to RX
FIFO. When disabled, a value of 0 for rx_control_del writes all
control words to RX FIFO. When enabled, a value of 1 deletes all
control words and only writes the data to the RX FIFO.
When you turn this option On, the 10G PCS includes the
rx_data_valid signal which Indicates when rx_data is valid.
This option is available when you select the following parameters:
Enable rx_10g_fifo_data_valid
port
On/Off
■
10G PCS protocol mode is Interlaken
■
10G PCS protocol mode is Basic and RX FIFO mode is
phase_comp
■
10G PCS protocol mode is Basic and RX FIFO mode is
register
Enable rx_10g_fifo_full port
On/Off
When you turn this option On, the 10G PCS includes the active
high rx_10g_fifo_full port. rx_10g_fifo_full is
synchronous to rx_clkout.
Enable rx_10g_fifo_pfull port
On/Off
When you turn this option On, the 10G PCS includes the active
high rx_10g_fifo_pfull port. rx_10g_fifo_pfull is
synchronous to rx_clkout.
Enable rx_10g_fifo_empty port
On/Off
When you turn this option On, the 10G PCS includes the active
high rx_10g_fifo_empty port.
Enable rx_10g_fifo_pempty port
On/Off
When you turn this option On, the 10G PCS includes the
rx_10g_fifo_pempty port.
On/Off
When you turn this option On, the 10G PCS includes the
rx_10g_fifo_del port. This signal is asserted when a word is
deleted from the RX FIFO. This signal is only used for the
10GBASE-R protocol.
On/Off
When you turn this option On, the 10G PCS includes the
rx_10g_fifo_insert port. This signal is asserted when a word
is inserted into the RX FIFO. This signal is only used for the
10GBASE-R protocol.
On/Off
When you turn this option On, the 10G PCS includes the
rx_10g_fifo_rd_en input port. Asserting this signal reads a
word from the RX FIFO. This signal is only available for the
Interlaken protocol.
On/Off
When you turn this option On, the 10G PCS includes the
rx_10g_fifo_align_val output port. This signal is asserted
when the word alignment pattern is found. This signal is only
available for the Interlaken protocol.
Enable rx_10g_fifo_del port
(10GBASE-R)
Enable rx_10g_fifo_insert port
(10GBASE-R)
Enable rx_10g_fifo_rd_en port
(Interlaken)
Enable rx_10g_fifo_align_val
port (Interlaken)
November 2012
Altera Corporation
Altera Transceiver PHY IP Core
User Guide