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12–36
Chapter 12: Stratix V Transceiver Native PHY IP Core
Standard PCS Interface Ports
Table 12–32. Standard PCS Interface Ports (Part 2 of 4)
Name
Dir
Synchronous to
tx_std_coreclkin/
rx_std_coreclkin
Description
Phase Compensation FIFO
rx_std_pcfifo_full[<n>-1:0]
Output
Yes
RX phase compensation FIFO full status flag. Valid
when the Phase Compensation FIFO is not in register
mode.
rx_std_pcfifo_empty[<n>-1:0]
Output
Yes
RX phase compensation FIFO status empty flag. Valid
when the Phase Compensation FIFO is not in register
mode.
tx_std_pcfifo_full[<n>-1:0]
Output
Yes
TX phase compensation FIFO status full flag. Valid
when the Phase Compensation FIFO is not in register
mode.
tx_std_pcfifo_empty[<n>-1:0]
Output
Yes
TX phase compensation FIFO status empty flag. Valid
when the Phase Compensation FIFO is not in register
mode.
Byte Ordering
rx_std_byteorder_ena
[<n>-1:0]
rx_std_byteorder_flag
[<n>-1:0]
Input
Output
No
Byte ordering enable. When this signal is asserted,
the byte ordering block initiates a byte ordering
operation if the Byte ordering control mode is set to
manual. Once byte ordering has occurred, you must
deassert and reassert this signal to perform another
byte ordering operation. This signal is an
synchronous input signal; however, it must be
asserted for at least 1 cycle of rx_std_clkout.
Yes
Byte ordering status flag. When asserted, indicates
that the byte ordering block has performed a byte
order operation. This signal is asserted on the clock
cycle in which byte ordering occurred. This signal is
synchronous to the rx_std_clkout clock. You must
a synchronizer this signal.
Byte Serializer and Deserializer
rx_std_byterev_ena[<n>-1:0]
Input
No
This control signals is available in when the PMA
width is 16 or 20 bits. When asserted, enables byte
reversal on the RX interface.
8B/10B
rx_std_polinv[<n>-1:0]
Input
No
Polarity inversion for the 8B/10B decoder, When set,
the RX channels invert the polarity of the received
data. You can use this signal to correct the polarity of
differential pairs if the transmission circuitry or board
layout mistakenly swapped the positive and negative
signals. The polarity inversion function operates on
the word aligner input.
tx_std_polinv[<n>-1:0]
Input
No
Polarity inversion, part of 8B10B encoder, When set,
the TX interface inverts the polarity of the TX data.
Altera Transceiver PHY IP Core
User Guide
November 2012 Altera Corporation