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7. Opcode and Sub-Instruction Structure
7
Opcode and Sub-Instruction
Structure
This section covers the assembler's opcode and sub-instruction structure.
7.1
Sub Instruction Types
Each ETPU opcode is split into one of the following four sub-instruction types.
ram
seq
alu
chan
7.2
Sub-Instruction groups
Multiple sub-instructions of the same type may be grouped together by separating the subinstructions with commas. Sub-instruction groups that contain one or more sub-instructions
are terminated by a semicolon, as follows.
chan clr_mrla, clr_mrlb.
Freescale Syntax
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Assembler Reference Manual, page 41