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The first argument for specifies the name of the new cell type. The
remaining arguments are pairs of connection types (in this example always
“bin”) and port names. Output ports must be prefixed with an asterisk
(*Y). The asterisk is only used when specifying the port in the celltype
command, not when referring to the port in other commands.
There is more to say about the celltype command but for this simple
example we don’t need any of the additional features that are described in
the later sections of this manual.
So far we have no means of communicating with the reconfigurable circuit
as we have not defined any inputs or outputs. As far as InterSynth is
concerned the input and output ports are just additional cell types:
!INa
!INb
!INc
!OUT
bin
bin
bin
bin
*X
*X
*X
X
AF
T
celltype
celltype
celltype
celltype
DR
In this example we are using different cell types for each individual input
cell. This way it is possible to distinguish between the input cells in the
netlists. If this is not required (e.g. because the inputs are interchangeable),
a single cell type can be used for all or a group of inputs.
The exclamation mark in front of the input and output cell names indicate that this cells don’t have an actual implementation that can be instantiated. The exclamation mark is not part of the cell type name and is
therefore only used in the celltype command and not when referring to
the cell type in other commands.
The commands input and output can be used to implement a wide
range of connections between the interior of the HDL module generated
by InterSynth with the outside world. In this example we only need the
simplest version of this commands:
input A 1 INa X
input B 1 INb X
input C 1 INc X
output Y 1 OUT X
The first argument to input or output declares the name that should be
used for the input or output signal in the generated HDL module. The 2nd
argument specifies the bit width of the signal and the 3rd and 4th argument
specify the cell type and cell port the signal should be connected to.
The only thing missing now are the example netlists. They are declared
using the commands “netlist” and “node”. E.g. an implementation of a
3-input AND would look like this:
3