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VP680 User Manual
r1.5
100MHz reference clocks connected to the FPGA in such a way that all MGT block can be
reached.
FPGA Pin
Net name
AD5
VPX_100M_REFCLK0n
AD6
VPX_100M_REFCLK0p
P5
VPX_100M_REFCLK1n
P6
VPX_100M_REFCLK1p
AK5
VPX_25M_REFCLK0n
AK6
VPX_25M_REFCLK0p
V5
VPX_25M_REFCLK1n
V6
VPX_25M_REFCLK1p
MGT REFCLK
MGTs reached
MGTREFCLK0_113
112, 113, 114
MGTREFCLK0_115
114, 115, 116
MGTREFCLK0_112
112, 113
MGTREFCLK0_114
113, 114, 115
Table 20: REF_CLK connections
Only one clock path is enabled, the other clock path is power down. Glue logic to control the
clock path is implemented in the CPLD. The FPGA controls clock path selection through
signal FP_CP_7 (see also Table 30).
FP_CP_7
Clock path selection
0
Clock path for 25MHz REF_CLK is selected
1
Clock path for 100MHz REF_CLK is selected
Table 21: Clock path selection
3.9.3 On-board MGT Reference Clock
A 100 MHz clock from an on-board low jitter oscillator is distributed to the FPGA using a jitter
attenuator. This clock can be used as the reference clock for the MGT blocks. The reference
clocks are connected in such a way that all MGTs can use these reference clocks.
FPGA Pin
Net name
AB5
LOCAL_REFCLK0n
AB6
LOCAL_REFCLK0p
M5
LOCAL_REFCLK1n
M6
LOCAL_REFCLK1p
MGT REFCLK
MGTs reached
MGTREFCLK1_113
112, 113, 114
MGTREFCLK1_115
114, 115, 116
Table 22: On-board MGT reference clock connections
3.9.4 FMC MGT Reference Clock
The FMC standard defines two high precision reference clocks that are driven from the FMC
to the carrier. The VP680 connects these clocks directly to MGT reference clock inputs. The
following table shows which MGTs can use these reference clocks.
UM004
VP680 User Manual
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