Download User Manual

B O A R D
H A R D W A R E
8 CPU Debug and CPU Trace
The DN6000K10S board includes two CPU debugging interfaces, the CPU Debug
(JP3 is a vertical header) and the Combined CPU Trace and Debug, (J5 is a vertical
mictor connector). These connectors can be used in conjunction with third party tools,
or in some cases the Xilinx Parallel Cable IV, to debug software as it runs on the
processor.
The PowerPC™ 405 CPU core includes dedicated debug resources that support a
variety of debug modes for debugging during hardware and software development.
These debug resources include:
•
Internal debug mode for use by ROM monitors and software debuggers
•
External debug mode for use by JTAG debuggers
•
Debug wait mode, which allows the servicing of interrupts while the processor
appears to be stopped
•
Real-time trace mode, which supports event triggering for real-time tracing
Debug modes and events are controlled using debug registers in the processor. The
debug registers are accessed either through software running on the processor or
through the JTAG port. The debug modes, events, controls, and interfaces provide a
powerful combination of debug resources for hardware and software development
tools.
The JTAG port interface supports the attachment of external debug tools, such as the
ChipScope™ Integrated Logic Analyzer, a powerful tool providing logic analyzer
capabilities for signals inside an FPGA, without the need for expensive external
instrumentation. Using the JTAG test access port, a debug tool can single-step the
processor and examine the internal processor state to facilitate software debugging.
This capability complies with the IEEE 1149.1 specification for vendor-specific
extensions and is, therefore, compatible with standard JTAG hardware for boundaryscan system testing.
8.1 CPU Debug
External-debug mode can be used to alter normal program execution. It provides the
ability to debug system hardware as well as software. The mode supports multiple
functions: starting and stopping the processor, single-stepping instruction execution,
setting breakpoints, as well as monitoring processor status. Access to processor
resources is provided through the CPU Debug port.
The PPC405 JTAG (Joint Test Action Group) Debug port complies with IEEE
standard 1149.1-1990, IEEE Standard Test Access Port and Boundary Scan
DN6000K10S User Guide
www.dinigroup.com
128