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“GC” clock inputs on the FPGA. These clocks can be used only by the FPGA that is associated
with the header. The GCC signal driven from each FPGA connects to a global clock buffer and
can be used by all of the FPGAs on the DN9000K10. See section 4.4 of this chapter for details
on GCC implementation and distribution.
Note that the GCC pin for DC10 (FPGA F16) does not go to a global clock network.
22.2.5 Timing and Clocking
Signal from the FPGAs to the daughtercard connector are not length-matched. The maximum
trace length on the DN9000K10 board for these signals is 800ps.
Each daughtercard has a global clock output pair DC*_GCCP/ DC*_GCCN. This LVDS
output is distributed on the DN9000K10 to all Virtex-5 FPGAs. The clock buffers on the host
board is designed to deliver the clock edge to all FPGA synchronized with the CCLK pin on the
daughtercard header. The daughtercard is expected to distribute clocks on it so that ICs on the
daughtercard receive the clock signal synchronized with the pin on the daughtercard header. In
this way, the host and daughter boards should be able to communicate synchronously with
equal, large IO periods in each direction.
There are three methods of communicating FPGA-to-FPGA across the daughtercard interface.
Local Synchronous
The daughtercard generates a clock and drives it over the GCAp/n or GCBp/n clock pins to
the host board FPGA. The daughtercard drives a synchronized clock to the logic on the
daughtercard, adding 0.5ns delay to account for the trace delay on the DN9000K10. The host
FPGA will use a DCM in zero-delay mode, and the logic on the daughtercard should have a low
clock-to-out and setup times (or use a DCM). This method has the disadvantage of only
allowing the one FPGA attached to the daughtercard to use this frequency. To communicate
globally across the DN9000K10, the user would have to pass the data across clock domains.
Global Synchronous
The daughter card generates a clock and drives it over the GCCp/n pins to the DN9000K10
host board. The user will select the daughtercard source for the daughter card network as
appropriate. Set the network in zero-delay mode (done by default). The disadvantage of this
method is that the DC GCLK network must be used. The advantage is that the entire system
can be operated on a single clock domain.
Zero-delay on the DN9000K10 is allowed by enabling PLL devices (zero-delay buffers)
connected to the GCC pins of each daughtercard header. To allow for a very wide range of
clock frequencies sourced from the daughtercard, the PLL bandwidth of these buffers must be
manually set. This can be done via USB or Compact Flash. The PLL can also be bypassed,
allowing a global system-synchronous clock to be used without configuring this PLL. To use
this method, the user will have to experimentally find the proper clock phase to use on the IO
of the daughter card.
DN9000K10 User Guide
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