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UM10732
NXP Semiconductors
Chapter 11: LPC11U6x/E6x USART0
Table 161. USART0 Line Status Register Read only (LSR, address 0x4000 8014) bit
description …continued
Bit
Symbol
2
PE
Value Description
Reset
Value
Parity Error. When the parity bit of a received character is in
0
the wrong state, a parity error occurs. A LSR read clears
LSR[2]. Time of parity error detection is dependent on FCR[0].
Note: A parity error is associated with the character at the top
of the USART0 RBR FIFO.
3
0
Inactive. Parity error status is inactive.
1
Active. Parity error status is active.
FE
Framing Error. When the stop bit of a received character is a
0
logic 0, a framing error occurs. A LSR read clears LSR[3]. The
time of the framing error detection is dependent on FCR0.
Upon detection of a framing error, the RX will attempt to
re-synchronize to the data and assume that the bad stop bit is
actually an early start bit. However, it cannot be assumed that
the next received byte will be correct even if there is no
Framing Error.
Note: A framing error is associated with the character at the
top of the USART0 RBR FIFO.
4
0
Inactive. Framing error status is inactive.
1
Active. Framing error status is active.
0
Break Interrupt. When RXD1 is held in the spacing state (all
zeros) for one full character transmission (start, data, parity,
stop), a break interrupt occurs. Once the break condition has
been detected, the receiver goes idle until RXD1 goes to
marking state (all ones). A LSR read clears this status bit. The
time of break detection is dependent on FCR[0].
BI
Note: The break interrupt is associated with the character at
the top of the USART0 RBR FIFO.
5
6
UM10732
User manual
0
Inactive. Break interrupt status is inactive.
1
Active. Break interrupt status is active.
Transmitter Holding Register Empty. THRE is set immediately 1
upon detection of an empty USART0 THR and is cleared on a
THR write.
THRE
0
Data. THR contains valid data.
1
Empty. THR is empty.
TEMT
Transmitter Empty. TEMT is set when both THR and TSR are
empty; TEMT is cleared when either the TSR or the THR
contain valid data.
0
Data. THR and/or the TSR contains valid data.
1
Empty. THR and the TSR are empty.
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 28 October 2015
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© NXP B.V. 2015. All rights reserved.
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