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Statements
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Example
The following example shows how to use assertion statements to report setuptime and pulse-width violations on a synchronous device.
ASSERT NOT (clock’event AND clock = ’1’ AND
preset = ’1’ AND NOT(preset’stable(20 ns)))
REPORT "Setup time violation" SEVERITY warning;
This statement asserts that when the clock changes to a high and the delayed
preset signal is a "one" and remains stable for 20 ns, the setup time is not in
violation. However, if the assertion fails, a "Setup time violation" warning is
generated.
ASSERT (preset’delayed = ’1’ AND preset = ’0’
AND preset’delayed’last_event >= 25 ns)
REPORT "Pulse width violation" SEVERITY warning;
The preceding example asserts that when preset changes from a high to a low and
the preset signal stays in the same state for at least 25 ns, the pulse width is not in
violation. If the assertion fails, a "Pulse width violation" warning is generated.
The items that follow the tic mark (’) are predefined signal attributes. For more
information on signal attributes, refer page 10-28.
Mentor Graphics VHDL Reference Manual, July 1994
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