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Download PCIeV4BASE User`s manual
Transcript
Bus transactions LW/R# ADS# BLAST# LAD[31:0] A D0 D1 D2 Dn-1 Dn PLX => FPGA CLK READY# LW/R# ADS# BLAST# FPGA drives LAD[31:0] LAD[31:0] A D0 D1 Dn-1 Dn FPGA => PLX CLK READY# Figure 11: Bus transactions with ReadBlock() and WriteBlock() in continuous burst mode This design supports the local bus continuous burst transfers as well as the single cycle transfers. For burst transfers the additional signal BLAST# (burst last) is needed, which is driven by the PLX PCIe controller. If this signal is asserted low, the PLX indicates the last LWORD it wants to transmit or receive. The FPGA can use the READY# signal for inserting wait states like in the single cycle mode. Furthermore the FPGA can drive the additional signal BTERM# (burst terminate) to break the current burst transfer and request a new address cycle. Note that the use of BTERM# is not demonstrated in “performance_test”, because it would decrease the performance. PCIEV4BASE / C1080-3807 User Doc V0.6 http://www.cesys.com/ -38- preliminary
