Download PCI334A Cabling

Transcript
PCI334A Features
PCI334A Features
MC68360 QUICC
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CPU32+ Processor (4.5 MIPS at 25 MHz)
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32-Bit Version of the CPU32 Core (Fully Compatible with the CPU32)
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Background Debug Mode
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Byte-Misaligned Addressing
Four General Purpose Timers
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Superset of MC68302 Timers
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Four 16-Bit Timers or Two 32-Bit Timers
Two Independent DMAs (IDMAs)
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Single Address Mode for Fastest Transfers
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Buffer Chaining and Auto Buffer Modes
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Automatically Performs Efficient Packing
System Integration Module (SIM60)
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Bus Monitor
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Double Bus Fault Monitor
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Software Watchdog
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Periodic Interrupt Timer
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Low Power Stop Mode
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Breakpoint Logic Provides On-Chip Hardware Breakpoints
Four Serial Communication Controllers (SCC)
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HDLC/SDLC™
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Signaling System #7 (SS7)
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Binary Synchronous Communication (BISYNC)
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Totally Transparent (Bit Streams)
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Totally Transparent (Frame Based with Optional Cyclic Redundancy Check (CRC))
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Asynchronous HDLC
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DDCMP™
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V.14
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X.21
Two Serial Management Controllers (SMC)
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UART
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Transparent
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General Circuit Interface (GCI) Controller
Communications Processor Module (CPM)
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RISC Controller
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224 Buffer Descriptors
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Supports Continuous Mode Transmission and Reception on All Serial Channels
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2.5 KBytes of Dual-Port RAM
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14 Serial DMA Channels
Four Baud Rate Generators
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