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ST10R272L - CENTRAL PROCESSING UNIT
the RETS and RETI instructions. On the acceptance of an interrupt, or the execution of a
software TRAP instruction, the CSP register is automatically set to zero
CSP (FE08h / 04h)
SFR
15
14
13
12
11
10
-
-
-
-
-
-
-
-
-
Bit
-
-
-
9
8
-
-
Reset Value: 0000h
7
6
5
-
4
3
2
1
0
SEGNR
-
r
Function
Segment Number
SEGNR
Specifies the code segment, from where the current instruction is to be fetched.
SEGNR is ignored when segmentation is disabled.
Code Segment
FF’FFFFH
15
CSP Register
0 15
IP Register
0
255
254
1
0
FE’0000H
01’0000H
24/20/18 bit Physical Code Address
00’0000H
Figure 12 Addressing via the code segment pointer
Note
When segmentation is disabled, the IP value is used directly as the 16-bit address.
The data page pointers DPP0, DPP1, DPP2, DPP3
These four non bit-addressable registers select up to four different data pages being active
simultaneously at run-time. The lower 10 bits of each DPP register select one of the 1024
possible 16-Kbyte data pages, and the upper 6 bits are reserved for future use. The DPP
registers give access to the entire memory space - in pages of 16Kbytes each.
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