Download PMC-CPU/440 - esd electronics, Inc.
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PMC-CPU/440 12 FPGA Status: preliminary Bits Name Function 8 LEDA_MODE When set to '1' LEDA (frontpanel) is controlled by CTRLB[LEDA]. When set to '0' LEDA is pulsed by an interrupt coming from an even (0,2,...) CAN IP core or by nIRQ1 from the FPGA's custom module. Default after reset: '1' 7..2 reserved unused -reads always 0 1 LEDB Controls the state of LEDB on the PMC's frontpanel when CTRLB[LEDB_MODE] bit is set to '1'. Default after reset: '0' 0 LEDA Controls the state of LEDA on the PMC's frontpanel when CTRLB[LEDA_MODE] bit is set to '1'. Default after reset: '0' 12.3.4 TSCTRL - Timestamp unit control register (0x0018) Bits Name Function (MSB) 31..5 reserved unused -reads always 0 5 TS_CFRSTEN Enable timestamp counter reset via IRIG-B control flags 4 TS_MRST Timestamp manual reset -write '1' to reset timestamp counter -reads always '0' 3 TS_XRSTEN Timestamp reset enable: '1': enable reset of timestamp counter via external RESET signal on Pn4 2..0 TS_SRC[2..0] Timestampcounter clock source select: '000': FPGA internal 100kHz clock '010': external CLOCK signal on Pn4 (other combinations of the TS_SRC bits are reserved for future use.) Note: Write 0x0000.0000 to TSCTRL for testing and read the current 64 bit counter value from offset 0x0010 and 0x0014. This uses the FPGA internal 100kHz timestamp clock source. 12.3.5 HOSTCTRL – Host control register (0x0060) Bits Name Function 31 .. 6 RESERVED Always read '0' 17 PMCRSTOUT_GATE see PMCRSTOUT_FLAG 16 PMCRSTOUT_FLAG This bit represents the state of PMC-RESETOUT# signal. After reset this bit is set. Clearing this bit can be used to assert the PMC RESETOUT# signal. The PMCRSTOUT_FLAG can only be modified when the PMCRSTOUT_GATE bit is set during the same write access to the HOSTCTRL register. This makes modification of the PMCRSTOUT_FLAG possible without read-modify-write operations and without taking care of the other bits of the HOSTCTRL register. 15 .. 8 RESERVED User Manual - V.2027.21 Filename: pmc440-me.odt Always read '0' Revision 1.1 2008-07-14 All rights reserved. Confidential! Copyright © esd gmbh 2008 Page 36 of 49