Download PMC-CPU/440 - esd electronics, Inc.

PMC-CPU/440
12 FPGA
Status: preliminary
12 FPGA
The PMC-CPU/440 comes with a Xilinx Spartan 3E FPGA (part#: XC3S1200E-4FTG256C) installed.
The FPGA provides several functions that are described in this chapter.
12.1 Functional Blocks
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IRIG-B
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decoding of B100 timecode format
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input source selection
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P4 rear differential input (default)
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P4 rear TTL input
local time code generation
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Multiple CAN IP cores (default: 2, max: 8)
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(CAN-) timestamping unit
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local time (64 bit counter) with 10us resolution
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timestamp latching for CAN
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free running counter, sync'ed to IRIG-B signal (digital PLL) or external clock
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default: external clock from Pn4
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resetable via register access or IRIG-B control function flag
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100kHz CLOCK_OUT + RESET_OUT generation on Pn4 for simple syncronisation of
external peripherals
Pn4 + frontpanel GPIO configuration
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usage as GPIO
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alternative functions (IRIG-B, timestamp syncing signals)
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Hardware FIFOs
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Custom module for customized extensions of the PMC-CPU/440
User Manual - V.2027.21
Filename: pmc440-me.odt
Revision 1.1
2008-07-14
All rights reserved. Confidential!
Copyright © esd gmbh 2008
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