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ComDeC
LSPM2
7 Timings
7.1 EEPROM
EEPROM READ cycle Op code 10 (example address 000 000b)
1
INTERCLK
INTERDOD
INTERCS
INTERDI
Startbit
1
2
1
2-bit Op code
2
3
4
5
6
Data
6-bit address
EEPROM READ cycle Op code 10 (example address 000 001b)
1
INTERCLK
INTERDOD
INTERCS
INTERDI
Startbit
1
Page 34
10/2002
min. 2µs
1
2
2-bit Op code
1
2
3
6-bit address
4
5
6
Data
The controller switches the signals to the pins with the trailing edge.
Release V2.0
User Description
Copyright (C) Siemens AG 2002. All rights reserved.