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Download TC1765 User`s Manual Peripheral Units
Transcript
TC1765 Peripheral Units General Purpose Timer Array (GPTA) 6.3.2.1 Clock Control Register The clock control register allows the programmer to adapt the functionality and power consumption of the GPTA module to the requirements of the application. The diagram below shows the clock control register functionality as is implemented in the TC1765 for the GPTA module. GPTA_CLC GPTA Clock Control Register 31 30 29 28 27 26 Reset Value: 0000 0002H 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RMC 0 0 FS OE SB WE E DIS SP EN DIS S DIS R rw r r rw w rw rw r rw 0 r 15 14 13 12 11 10 9 8 Field Bits Type Description DISR 0 rw Module Disable Request Bit Used for enable/disable control of the module. DISS 1 r Module Disable Status Bit Bit indicates the current status of the module. SPEN 2 rw Module Suspend Enable for OCDS Used for enabling the suspend mode. EDIS 3 rw External Request Disable Used for controlling the external clock disable request. SBWE 4 w Module Suspend Bit Write Enable for OCDS Defines whether SPEN and FSOE are write protected. FSOE 5 rw Fast Switch Off Enable Used for fast clock switch off in OCDS suspend mode. RMC [15:8] rw 8-Bit Clock Divider Value in RUN Mode 0 7, 6, r [31:16] Reserved; returns 0 if read; should be written with 0. Note: After a hardware reset operation the GPTA module is disabled. User’s Manual 6-147 V1.0, 2002-01
