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13.11.2 Interrupt Register
The QADC64 interrupt register QADC64INT specifies the priority level of QADC64
interrupt requests
The values contained in the IRL1 and IRL2 fields in QADC64INT determine the priority
of QADC64 interrupt service requests.The interrupt levels for queue 1 and queue 2
may be different.
13.11.3 Interrupt Levels and Time Multiplexing
The QADC64 conditionally generates interrupts to the bus master via the IMB IRQ signals. When the QADC64 sets a status bit assigned to generate an interrupt, the
QADC64 drives the IRQ bus. The value driven onto IRQ[7:0] represents the interrupt
level assigned to the interrupt source. Under the control of ILBS, each interrupt request
level is driven during the time multiplexed bus during one of four different time slots,
with eight levels communicated per time slot. No hardware priority is assigned to interrupts. Furthermore, if more than one source on a module requests an interrupt at the
same level, the system software must assign a priority to each source requesting at
that level. Figure 13-11 displays the interrupt levels on IRQ with ILBS.
IMB3 CLOCK
ILBS [1:0]
00
IMB3 IRQ [7:0]
01
IRQ
0:7
10
IRQ
8:15
11
00
01
IRQ
16:23
IRQ
24:31
IRQ
0:7
10
11
Figure 13-11 Interrupt levels on IRQ with ILBS
13.12 Programming Model
Each QADC64 occupies 1 Kbyte (512 16-bit entries) of address space. The address
space consists of ten 16-bit control, status, and port registers; 64 16-bit entries in the
CCW table; and 64 16-bit entries in the result table. The result table occupies 192 16bit address locations because the result data is readable in three data alignment
formats.
Table 13-6 shows the QADC64 memory map. The lowercase “x” appended to each
register name represents “A” or “B” for the QADC64_A or QADC64_B module, respectively. The address offset shown is from the base address of the module. Refer to 1.3
MPC555 Address Map to locate each QADC64 module in the MPC555 memory map.
MPC555
USER’S MANUAL
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Revised 15 September 1999
MOTOROLA
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