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KS32C50100 RISC MICROCONTROLLER ETHERNET CONTROLLER MAC Received Pause Count Register The received Pause count register, EPZCNT, stores the current value of the 16-bit received Pause counter. Table 7-38 EPZCNT Register Register EPZCNT Offset Address R/W 0xA040 R Description Pause count Reset Value 0x00000000 Table 7-39 Received Pause Count Register Description Bit Number [15:0] Bit Name Description Received Pause count (EPZCNT) The count value indicates the number of time slots the transmitter was paused due to the receipt of control Pause operation packets from the MAC. MAC Remote Pause Count Register The remote Pause count register, ERMPZCNT, stores the current value of the 16-bit remote Pause counter. Table 7-40 ERMPZCNT Register Register ERMPZCNT Offset Address R/W 0xA044 R Description Remote pause count Reset Value 0x0000000 Table 7-41 Remote Pause Count Register Description Bit Number [15:0] Bit Name Remote Pause count (ERMPZCNT) Description The count value indicates the number of time slots that a remote MAC was paused as a result of its sending control Pause operation packets. 7-49
