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UART
KS32C50100 RISC MICROCONTROLLER
31
8
7
6
5
4
3
2
1
0
T R D B
F P O
T
B D T K
E E V
C
E R R D
[0] Overrun error (OV)
0 = No overrun error during receive
1 = Overrun error (generate receive status interrupt if UCON[2] is 1)
[1] Parity error (PE)
0 = No parity error during receive
1 = Parity error (generate receive status interrupt if UCON[2] is 1)
[2] Frame error (FE)
0 = No frame error during receive
1 = Frame error (generate receive status interrupt if UCON[2] is 1)
[3] Break detect (BKD)
0 = No break received
1 = Break received (generate receive status interrupt if UCON[2] is 1)
[4] Data terminal ready (DTR)
0 = DTR pin (nUADTR) is High
1 = DTR pin (nUADTR) is Low
[5] Receive data ready (RDR)
0 = No valid data in the receive buffer register
1 = Valid data present in the receive buffer register
(issue interrupt or DMA request if UCON[1:0] is set)
[6] Transmit buffer register empty (TBE)
0 = Valid data in transmit holding register
1 = No data in transmit holding register
(as the setting of UCON[4:3], interrupt or GDMA request is generated.)
[7] Transmit complete (TC)
0 = Transmit in progress
1 = Transmit complete; no data for Tx
Figure 10-4 UART Status Registers
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