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ETHERNET CONTROLLER KS32C50100 RISC MICROCONTROLLER Timing Parameters for MII Transactions The timing diagrams in this section conform to the guidelines described in the "Draft Supplement to ANSI/IEEE Std. 802.3, Section 22.3, Signal Characteristics." Tx_clk 0 ns MIN, 25 ns MAX TxD [3:0], Tx_en Figure 7-25 Transmit Signal Timing Relationship at MII Rx_clk 10 ns MIN RxD [3:0], Rx_DV, Rx_er 10 ns MIN INPUT VALID Figure 7-26 Receive Signal Timing Relationship at MII 7 Cycles 7 Cycles MDC 0 ns MIN, 300 ns MAX MDIO Figure 7-27 MDIO Sourced by PHY MDC 10 ns MIN MDIO 10 ns MIN INPUT VALID Figure 7-28 MDIO Sourced by STA 7-66
