Download CPU Read/Write Access 4 LANCE Interrupt Status 4 Read

Contents
Ethernet Expansion Board
1
Ethernet Interface
3
Interface I/O Description
3
Status and Command Circuitry
CPU Read/Write Access
LANCE Interrupt Status
Read/Write Control Register
4
4
4
4
State Machine Control Circuitry
4
LANCE Interface
6
Ethernet Interface
6
Software Interface
Expansion Slot
On-Board Addressing
6
7
7
Contents
Interface Registers and Command
Descriptions
ID Register (Base Address
03FFFF - 03FFCO)
7
8
Software Reset
LANCE Data Latch
Status Ring Address
Control Register
LANCE Register Address and Data
Ports
8
9
9
9
10
Software Operation
10
Troubleshooting
11
I/O Cycle
Register Read/Write Cycle
Board ID Read-Only Cycle
CPU LANCE Read/Write Cycle
11
13
14
14
DMA Cycle
DMA Read/Write (Single)
DMA Read/Write (Burst)
14
15
17
Interrupt Cycle
17
Contents
Figures
1
2
3
4
5
6
7
8
9
Expansion Board Block Diagram
Ethernet State Diagram
Expansion Board Cycle Diagram
CPU non-LANCE Read-Timing
Diagram
........................... ':;:11
CPU non - L ..~.NCE lA]y-;+-=-'T';TTl;-nrr
""'.&.
Diagram
CPU LANCE Read-Timing Diagram
CPU LANCE Write-Timing
Diagram
LANCE DMA Read Cycle
LANCE DMA Write Cycle
2
12
16
18
...L ' - " " "
19
20
21
22
23
Tables
1
2
3
Ethernet IS-Pin D Connector
Expansion Slot Offset
Addresses
State Assignments
6
7
13
Ethernet Expansion Board Theory of Operation
This overview summarizes the major functions performed by the
UNIX™ PC Ethernet Expansion Board hardware. The topics covered
here include:
o
Interface I/O description
o
Status and command circuitry
o
State machine control circuitry
o
LANCE interface
o
Ethernet interface
o
Software interface
Ethernet ExPansion Board
The Ethernet Expansion Board (EEB), when plugged into an AT&T
UNIX™ PC, provides an interface to an Ethernet communications
network operating at a transfer rate of 10MB/sec. The EEB is
based on the AMD 7990 and 7992 chip set, which performs the
following functions:
o
AM7990 Local Area Network Controller for Ethernet (LANCE)
performs memory management, packet handling, error reporting,
and interface functions.
o
AM7992 Serial Interface Adapter (SIA) performs Manchester
encoding and decoding of the serial bit stream with phase
lock loop, clock recovery.
The Expansion Board, as shown in the Figure 1 block diagram, is a
circuit board containing the I/O and DMA interface to the Lm~CE
chip, a state machine with a read/write control register, a
separate DMA controller for LANCE status, and a board ID/Ethernet
address ROM.
1
XR/w*, XIOEN *
BUFFER
XRST*
EXPRQ EXPBG * XR/W* OS * INT*
BUFFER
BUFFER
STATUS
RING
ADDRESS
AND
DATA
SYSTEM
CONTROLLER
o
INT*, HOLD*, RDY*, DAS* LAS*
I"'tI
HLDA*,RDy*,DAS*, LAG*
RECEIVE
BUFFER
AMD7990
LANCE
BUFFER
TRANSMIT
~
~
Figure 1
Expansion Board Block Diagram
AMD7992
SERIAL
INTERFACE
ADAPTOR
DC-DC
CONVERTER
~COLL.,
t.- XMIT,
REC.
~
12V.
GND
Ethernet Expansion Board Theory of Operation
Once the LANCE chip is initialized, all data transfers including
buffer chaining are handled by the chip.
Timing and control are
maintained by the on-board state machine.
LANCE status is
transferred to memory by a separate state machine DMA controller
on each LANCE interrupt. This status is placed in a 256-word
ring in memory allowing the software a 256-packet interrupt
latency.
Because of maximum throughput, the CPU is able to find
all data and status in memory and never needs to talk directly to
the board. The board is also not re~~ired to wait for CPU
response or to share board resources with the CPU accesses.
LANCE operation consists of two distinct modes, transmit and
receive.
In the transmit mode, the LANCE chip directly accesses
data in memory. Data is conditioned by adding a preamble, sync
pattern, and appending a 32-bit cycle redundancy check (eRe)
This packet is sent from the LANCE to the AM7992A Serial
Interface Adapter (SIA). The SIA then transmits this packet to
the Ethernet system AM7995 transceiver.
In the receive mode,
packets are sent by the SIA to the LANCE.
Ethernet Interface
The Ethernet system, to which the EEB is connected, consists of
an external AM7995 transceiver with power supply and the Ethernet
coax transmission line. The EEB is connected to this system by
cable. For a detailed description of the Ethernet system
interface, refer to the Ethernet/IEEE 802.3 specification and
the technical manual for Local Area Network Controller AM 7990
(LANCE) by Advanced Micro Devices.
Interface I/O Descrtption
The expansion-board interface consists of drivers and receivers
for all required signals to and from the UNIX PC's expansion bus.
The expansion data bus goes through buffers that are controlled
by the state machine section to create the internal data bus.
The address bus and the bus cycle control signals are received
with buffers that are always enabled to create the internal
address and control bus. The internal address and control bus,
with the comparator for board ID, allows constant monitoring for
board I/O requests, which are then passed on to the state
machine.
For board-initiated DMA cycles, the state machine-generated
request, read/write, and data strobe signals are also driven onto
the expansion bus by this section.
3
Ethernet Expansion Board Theory of Operation
Status and Command Circuitry
The amount of on-board status and command information is limited.
The board ID function has been expanded to allow the CPU to
interrogate the board for the 6-byte Ethernet address, as well as
for the required 4-byte board ID. This information is contained
in a 32-byte prom accessed at odd byte addresses in the upper 32
bytes of the board address block. A write to any of these
addresses produces a board reset.
CPU Read/Write Access
The status and command section provides CPU read/write access to
the LANCE chip address and data ports. However, due to the long
access time of the chip, LANCE reads do not provide data to the
CPU in a single cycle. Data is latched on board during the LANCE
read; it is then read by the CPU in a separate latch read cycle.
LANCE Interrupt Status
This section contains a 16-bit register and an 8-bit counter.
The LANCE interrupt status is written automatically to memory at
the location of the combined 24-bit address by the on-board DMA.
Read/Write Control Register
A 4-bit read/write control register is also contained in this
section. This register allows the CPU to disable DMA for
diagnostic purposes, select Ethernet, and make selections between
INT 01 and INT 05. The register contains one unused bit.
State Machine Control Circuitry
The state machine control section consists of five PALs providing
control and timing signals for all other sections. A 20R8 PAL
determines when a board cycle needs to be initiated and what type
of cycle it should be. The 20R8 arbitrates between LANCE DMA
requests (HOLD), LANCE interrupts, and CPU I/O requests and
generates the LANCE HLDA and expansion bus requests as well as onboard I/O cycles.
4
Ethernet Expansion Board Theory of qperation
Each of 11 non-idle cycles has its own timing and control
requirements (see timing diagrams for more detail).
These cycles
consist of five CPU-initiated operations which are:
o
CPU non-LANCE Read
o
CPU non-LANCE Write
o
CPU LANCE Read
o
CPU LANCE Write
o
CPU Data Latch Read
These are all individual cycles that can occur only when the
state machine is in its idle state.
The state machine is always
returned to the idle state.
Three additional cycles are initiated by LANCE DMA requests.
These are:
o
request cycle
o
LANCE DMA read cycle
o
LANCE DMA write cycle
The request cycle precedes a single LANCE DMA cycle or burst of
cycles.
This cycle insures UNIX PC LANCE synchronization.
The
LAl~CE D~~ read or write cycles follow the request cycle.
Lne
state machine goes directly from the request cycle to the read or
write without going through idle. As long as the LANCE DMA
request stays active, each DMA cycle leads directly to the next,
again without idle.
LANCE DMA requests are either single cycle
for buffer management fetches or bursts of eight cycles for data
transfers.
The three final cycle types are also linked together with no
intervening idle states.
When the LANCE asserts its interrupt
the state machine executes a status LANCE read cycle reading the
LANCE interrupt status into the on-board data latch.
A status
DMA cycle is executed to place the status in the status ring in
memory.
Finally, a status LANCE write is executed to clear the
LANCE interrupt, and a CPU interrupt is generated at the same
time.
5
Ethernet Expansion Board Theory of Operation
The 20R8 PAL encodes the cycle type in 4 bits. These 4 bits are
fed to three additional registered PALS. These signals combine
with a 3-bit counter for timing within each cycle and, with
several handshake signals from the LANCE, allowing these three
PALS to generate all LANCE-related timing and control signals.
In addition, an I/O cycle signal is generated for on-board nonLANCE cycles. This signal goes to the fifth PAL. This PAL is a
nonregistered PAL that generates timing and control for on-board
I/O that is based on I/O cycle and address decodes.
LANCE Interface
The LANCE interface consists of a 16-bit, multiplexed address and
data bus with associated handshake signals. The hardware
provides three sets of 16-bit latches for address, read data, and
write data. This section also includes a buffer for the upper 5
bits of address and a 4-bit data buffer. These buffers provide
for the status write to clear the LANCE interrupt.
Ethernet Interface
The Ethernet interface is handled by the AMD chip set. The LANCE
chip sends transmit data to the 7992 and gets receive data and
collision detection from the 7992. The 7992 provides the
interface to the off-board transceiver through a standard IS-pin
D-connector interface. Table 1 lists the pin-out assignments for
this connector.
Table 1
Signal
Pin
1
2
3
4
5
GND
I
COL+
TRANS +
Not Used
RCVR+
Ethernet 15-Pin D Connector
Pin
6
7
8
9
10
Signal
GND
Not Used
Not Used
COLTRANS-
Pin
11
12
13
14
15
Signal
Not Used
RCVRPLUS12
Not Used
Not Used
Software Interface
The EEB occupies the standard 2S6Kbyte (or 128K word) block
assigned to each expansion slot.
6
Ethernet Expansion Board Theory of Operation
Expansion Slot
The expansion cards in the u~IX PC are each assigned 256K bytes
of address space.
Since all addressing is done on word
boundaries, 128K words of address space is available.
Expansion
bus address bits XAI - XA17 define this space.
Each expansion
slot contains hardwired identification bits XIDO - XID2 to define
seven unique slot addresses.
Bits XA18 - XA20 are compared
against the slot identification bits to validate the address.
Also, address bit XA21 is always zero;
similarly, expansion
addresses XA22 and XA23 are always ones.
Therefore, once the EEB is plugged into its slot, the
predetermined XA18 - XA23 bits generate the offset address, while
devices.
The offset addresses used in the UNIX PC are listed below.
Table 2
Expansion Slot Offset Addresses
Slot Number
Offset Address (h)
0
1
2
3
OCOOOOO
OC40000
OC80000
OCCOOOO
ODOOOOO
OD40000
OD80000
ODCOOOO
4
5
6
7
On-Board Addressing
Only a small number of addresses are decoded for on-board
functions.
These addresses are not fully decoded in hardware.
Undefined addresses should not be used; they may affect on-board
functions.
Reads and writes are always full words, even if only
8-bit values are significant.
Interface Registers and Command Descriptions
The following paragraphs list the registers used in Ethernet
interface operations and the command descriptions that select the
I/O functions.
7
Ethernet Expansion Board Theory of Operation
ID Register (Base Address 03FFFF - 03FFCO)
When the UNIX PC is first powered up, the UNIX kernel reads the
ID register into memory.
The ID register is a set of 8-bit
registers located at odd byte addresses in the upper 32 words of
the board address block.
The upper four words contain the
required board identification numbers.
The lowest six words
contain the board-specific Ethernet station address.
The
appropriate driver must determine where the hardware is located.
The getslot system call (see UNIX System V User's Manual,
drivers(7»
locates the offset (slot).
The base address is then
added to the offset address to access the appropriate registers.
Base Address
Description
03FFFF
03FFFE
03FFFD
R
03FFFC
03FFFB
03FFFA
R
R
R
R
R
MSB of ID, two's complement
Not Used
LSB of ID less than two's
complement
Not Used
MSB of ID
through
03FFCD
03FFCC
03FFCA
03FFC9
03FFC8
03FFC7
03FFC6
03FFC5
03FFC4
03FFC3
03FFC2
03FFCI
03FFCO
R
R
R
R
R
R
R
R
R
R
R
R
Not Used
MSB Ethernet Address
Not Used
Ethernet Address
Not Used
Ethernet Address
Not Used
Ethernet Address
Not Used
Ethernet Address
Not Used
LSB Ethernet Address
Not Used
Software Reset
A write to any of the four board ID addresses causes the board to
be reset and put into an inactive state.
Base Address
03FFFF
03FFF8
8
R/W
W
through
W
Description
Software Reset
Software Reset
Ethernet Expansion Board Theory of Operation
LANCE Data Latch
This read-only, 16-bit latch is re~~ired to acco~~odate the slow
LANCE register access time to the expansion-board timing
requirements through a two-step process. Reading the on-chip
LANCE registers does not produce valid data in time for the
active I/O cycle, but the data is stored in the LANCE data latch.
Subsequently, a read of the latch will return the desired data to
the CPU.
Base Address
000006
Description
R
LANCE Data Latch
Status Ring Address
This write-only, 16-bit register is used to supply bits A9 to A21
of the status ring address.
Bits Al to A8 are supplied by an onboard counter which is cleared on reset.
Together, they supply
the addressing for the on-board DMA to place LANCE status in
memory automatically. A write to this address clears any pending
interrupts.
Base Address
000006
Description
w
Status Ring Address
Control Register
The board contains a read/write, 4-bit control register to
provide selection of interrupt line, LAN interface type, and a
DMA disable for diagnostic purposes. This register is reset to
zeros by hardware or software reset.
Bit
Signal
Description
DO
DMAEN
1
0
DMA Enabled
DMA Disabled
D1
RESERVED
1
a
Other Selected
Ethernet Selected
1
0
Use Interrupt 01
Use Interrupt 05
D2
INTSEL
D3
SPARE
9
Ethernet Expansion Board Theory of Qperation
A read of this address also resets the board interrupt.
Base Address
R/W
000004
RW
Description
Control Register
LANCE Register Address and Data Ports
The LANCE chip in slave mode contains two ports. The register
address port is a 2-bit port that selects which of the four 16-bit
control and status ports are accessed through the register data
port.
Base Address
R/W
Description
000002
RW
LANCE Register Address Port
000000
RW
LANCE Register Data Port
Software Operation
Once the LANCE chip has been started, all data and status
transfers are done through DMA. No I/O access is permitted to
the board except the software reset and interrupt reset
functions.
10
Ethernet Expansion Board Theory of Qperation
Troubleshooting
The following procedures are a simplified description for
troubleshooting a UNIX PC Ethernet Expansion Board that is not
functioning properly or has failed a diagnostics test. The
following items are required to perform these procedures:
o
o
o
o
Kernel debugger program
An Oscilloscope
Voltmeter (VOM)
Logic Analyzer
The following reference books will also be useful:
o
Ethernet Board Installation and Diaanostics Guide
o
Advanced Micro Devices Local Area Network Controller AM799Q
(LANCE) Technical Manual
Before beginning with the troubleshooting procedures, check the
schematic against the ICs on the board so they can be identified
readily. Also, during operation of the expansion board, the
voltage at J2-13 should be 12 - 13 Vdc.
Troubleshooting is concerned with the EEB's three basic cycles
and how they relate to components that have failed.
Figure 2 is
a diagram of the Ethernet states and Table 3 lists the state
assignment functions during specific cycles. These cycles are:
o
o
o
I/O cycle
DMA cycle
Interrupt cycle
1/0 Cycle
The I/O cycle consists of three individual cycles as follows:
o
o
o
Register Read/Write cycle
Board ID Read-Only cycle
CPU LANCE Read/Write cycle
When the EEB has been reset either by a hardware or software
reset, it is at the idle state. By using the Kernel debugger
program, the I/O cycle can be examined for the three read and
write functions listed above. A failure of any of these cycles
indicates the following hardware problems:
11
Ethernet Expansion Board Theory of Operation
IDLE
Figure 2
12
Ethernet State Diay.l am
Ethernet Expansion Board Theory of Operation
Table 3
State Assignments
Cycle
3
.2
1
Function
0
0
0
0
0
IDLE
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
STLRD
STLWR
CPUREGRD
0
1
1
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
1
1
CPULRD
CPULWR
LDMARD
LDMAWR
STDMAWR
IORDCYC
IOWRCYC
RQCYC
Register Read/Write Cycle
A failure of this cycle is a result of a malfunctioning PAL or
wrong PAL equation, a cycle status being misread to the state
machine, or a clock failure.
The following components should be
checked for the listed conditions:
o
4B (PAL16L8A located on schematic page 4) is either
malfunctioning or the wrong equation is being read.
o
4C (PAL20R8A located on schematic page 5) is either
malfunctioning or the wrong equation is being read.
Also,
use the logic analyzer to check pins 19 - 22 for the correct
CYCO* - CYC3* sequence (refer to the cycle diagram, Figure 3) .
o
4C - 4F (PAL20R8A, PAL16R8A, PAL16R6A, and PAL16R8A located on
schematic sheet 5) are not receiving clock signals on pin 1.
13
Ethernet Expansion Board Theory of Operation
Board ID Read-Only Cycle
The following components should be checked for failure:
o
2F (PROM 748288 or 823123 located on schematic sheet 4) has
failed.
o
4B (PAL16L8A located on schematic sheet 4) has failed.
o
There is no clock present.
CPU LANCE Read/Write Cycle
The LANCE location address is being accessed by writing to the
Register Address Pointer (RAP).
The CPU LANCE Read cycle is
performed in two steps.
First, location 0000 is read; second,
location 0006 is read-returning the valid data from the address
pointed to by RAP.
If the CPU LANCE Read/Write cycle fails, check the following
components for the listed conditions:
o
4C (PAL20R8 located on schematic sheet 5) the pin 19 - 22,
CYCO* - CYC3* is not correct.
o
4E (PAL16R6A located on schematic sheet 5) is not providing
the proper signal interface (DA8* and READY*) to the LANCE.
o
4H (AM 7990 LANCE located on schematic sheet 3)
malfunctioning.
is
DMA Cycle
The DMA cycle consists of three individual cycles as follows:
o
o
o
DMA Read (single or burst) cycle
DMA Write (single or burst) cycle
8TATUS DMA Write (single) cycle
A failure of any of these cycles indicates the following hardware
problems as discussed in the following paragraphs.
14
Ethernet Expansion Board Theory of Operation
DMA Read/Write (Single)
On the first two cycles, DMA Read and DMA Write, the address is
provided by LANCE.
For STATUS DMA Write, the address comes from
the on board registers 1G and IE, and ring counters 2B and 2C,
located on schematic page 4.
These are written to during
initialization.
The LANCE performs 12 single DMA READ cycles when a 1 is being
written to the initializing bit of the LANCE control-status
register.
Using a logic analyzer, check 5D, pin 8 (RQ) located
on schematic page 4, for these 12 requests corresponding to bus
grant (BG) from 1H, pin 16 with 1A pin 12 (XR/W*) high.
111cr'\
.I. I...L.""'" '-J ,
0
0
0
0
0
check the signal
4H
4H
4H
4H
4H
pin
pin
pin
pin
pin
17
19
18
14
22
+-;YY\;Y""I"'"
'-...L..1ll...L.J.J.~
at
T J\ ....Tr~
..L..J.ILJ." v .....
as
~"...,
,
"... .. Y'~.
.LV.L.LVWi:> •
(HOLD*) schematic page 3
(HLDA*)
(LAS*)
(DAS*)
(READY*)
Refer to the timing diagram in Figure 3.
After initialization, LANCE generates the interrupt active low at
4H pin 11. The state machine gets the status from the LANCE and
writes to the status ring.
The content is 01C1 (see the bit
definition in the LANCE technical manual).
The state machine
then generates the interrupt to the CPU at the same time that it
writes Is to the LANCE, clearing the LANCE interrupt and status.
If the initialization is complete and correct, the status content
at the CPU memory will be 01C1.
15
Ethernet Expansion Board Theory of Operation
COMPONENT
SIGNAL
(LANCEI
HOLD*
(4CI
HLDA *
(LANCEI
LAS*
(LANCEI
DAS*
r4EI
READY *
r4CI
RQ
iCPU,
8G
~
500 ns
~
XRIW*
Figure 3
Expansion Board Cycle Diagram
Next, the LANCE performs a single DMA read to the TMD1 every 1.6
msec.
Using the oscilloscope, check the RQ and Be activity.
Be
should have a 500 nsec pulse width. RQ should be gone 100 nsec
after Be is active.
If there is no activity (neither RQ nor BG)
check if HOLD*, HLDA*, LAS*, DAS*, READY*, and CYCO through CYC3*
are generated from 4C, located on schematic page 5.
The cycle should not be stuck at DMA Read longer than 3 us.
If
it is, this indicates that 4C and 4E on schematic page 5 or the
LANCE is defective.
16
Ethernet Expansion Board Theory of Operation
DMA Read/Write (Burst)
Using a logic analyzer, observe the DMA Read/Write burst.
The
burst should consist of a transfer of 8 words, except for the
last cycle if data is fewer than 8 words.
If the DMA Read/Write
burst does not perform properly, check 4C and 4E on schematic
page 5, or the LN~CE.
Interrupt Cycle
The interrupt cycle consists of the LANCE sending an interrupt to
the state machine at the completion of an operation.
If there is
an error, the state machine reads the LANCE status and requests
that the status DMA Write cycle be performed.
Once the state
machine gets the bus, it writes to the location of the current
status ring address and updates the status ring address.
Then
the state machine generates the interrupt to the CPU.
Note that
the status ring content normally shows whether the problem is in
either reception or transmission of data.
Check the receive or
transmit descriptor ring for further status information.
17
XO
X1
X2
X3
X4
X5
X6
X7
X8
X9
X10
X11
X13
X12
X15
X14
X16
X17
X18
X19
XO
XPCK+
~~~~___________________________________________________________________________~~
XIOEN*
XA(21:01)
~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _._V_A_L_ID_A_D_DR_E_S_S_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
XR/W*
•
~
o
2
3
4
5
6
CYCLE END
CYCLE*
I/O READ CYCLE
XCVDIR
XCVOE*
~~---------------------------~
~-------------------------------------~~
~
XD(15:00)
____________
VA_L_I_D_D_A_TA
_____________
Figure 4
CPU non-LANCE Read-Timing Diagram
o
HI
XO
XPCKt
XIOEN*
X1
X2
X3
X4
X5
X6
X7
X9
X8
X10
X11
X12
X14
X15
X16
X17
X18
X19
XO
~
~~""""~___________________________________________•________________________________
XA(21:01)
~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.______________V_A_Ll_D_A_D_D_R_ES_S______________
XR/W*
~ ________________________________________________._________________
o
3
2
5
4
CYCLE*
I/O WRITE CYCLE
XCVDR
_r
XCVOE*
XD(15:00)
10CYC*
D(15:00)
---~~_________________•___________V_A__Ll_D_D_A_TA_,_ _ _ _ __
~~----------------.----------
~~U
___________________
_~,-______._ _ _ _ _ _._ _ _ _ _ _ _ _ _ _V_'A_L_ID_D_A_TA_._ _ _ _ _ _ _,
o
M
Figure 5
CPU non·-LANCE Write-TimjLng Diagram
t-.J
tT1
0
~'1
XO
X1
X2
X3
X4
CYCLE*
•
X6
X19
X18
XO
X1
X13
X14
X15
X16
X17
X18
~
CD
X19
rt
NN1JLI1NN
XPCLK+
XIOEN*
X5
•
NN
NN
~
tT1
~
~
til
NN
~.
0
~
ICYCLE
NN
~
CPU LANCE READ
NN
ENol
NN
t.'d
0
IlJ
'1
~
LCS*
~
NN
~
NN
~
0
~
LOUTLE*
NN
0
to;,
REAO*
NN
~
CD
'1
OAS*
IlJ
rt
~.
NN
REAOY*
~
NN
OAL(15:00)
Figure 6
600 OR
~
1400
0
~
~IN
NN(
VALID DATA
CPU LANCE Read-Timing Diagram
)
X2
X3
X4
X5
X6
X7
X8
X9
X10
X11
X19
X1
X11
X12
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