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ML671000 User’s Manual
Chapter 12 External Memory Controller (XMC)
12.2.12. Refresh Timer Counter (RFTCN)
This 8-bit read/write register is the counter for generating CAS-before-RAS (CBR) refresh requests.
It counts clock cycles from the time base generator (TBG) down from the starting value specified by
the refresh cycle control register (RCCON).
Writing “1” to either CBRR bit in the refresh control register (RFCON) loads this register from
RCCON and starts the countdown.
When the contents reach 0x00, the hardware initiates a DRAM CAS-before-RAS refresh cycle.
When this refresh cycle is complete, the hardware reloads this register from RCCON and restarts the
countdown.
After a system reset, the contents are 0xFF.
7
6
5
4
3
Figure 12-14
2
1
0
Refresh Timer Counter (RFTCN)
12.2.13. Refresh Cycle Control Register (RCCON)
This 8-bit read/write register specifies the cycle interval for generating CAS-before-RAS (CBR)
refresh requests. The hardware loads the contents of this register into the refresh timer counter
(RFTCN) when the program writes “1” to a CBRR bit in the refresh control register (RFCON) or the
previous refresh operation is complete.
After a system reset, the contents are 0xFF.
7
6
5
4
Figure 12-15
12-18
3
2
1
0
Refresh Cycle Control Register (RCCON)