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Document type:
User's Manual (MUT)
Title:
Mod. V2718 VME PCI Optical Link Bridge
2.13.8.
Revision date:
18/12/2008
Revision:
8
Input register
(Base Address + 0x08, D16, read/write)
This register carries the input register pattern.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IN0
IN1
IN0_OR_IN1
PLSA_OUT
PLSB_OUT
SCR_END_CNT_PLS
LMON
Fig. 2.9: Input register
2.13.9.
Output set register
(Base Address + 0x0A, D16, read/write)
This register allows to set the output register pattern: 1 = set; 0 = leave previous setting
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PLSA_START
PLSA_RESET
PLSB_START
PLSB_RESET
SCR_GATE
SCR_RESET
OUT0
OUT1
OUT2
OUT3
OUT4
Fig. 2.10: Output set register
NPO:
00106/03:V2718.MUTx/08
Filename:
V2718_REV8.DOC
Number of pages:
66
Page:
21