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e500 TLBs and Translation
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Based on the setting of the SIZE field of the matching TLB entry, the RPN field
replaces the corresponding most-significant n bits of the effective address.
MSR[DS] for data access
MSR[IS] for instruction fetch
32-bit Effective Address
PID0
AS
PID1
PID2
0
Effective Page Number (EPN) Offset
n–1 n
31
Three 41-bit Virtual Addresses (VAs)
TLBs
RPN field of matching entry
0
Offset
Real Page Number (RPN)
n–1 n
31
NOTE: n = 32 – log2 (page size)
32-bit Real Address
This diagram shows how the address bits get translated with the e500 MMU.
Since there are variable page sizes, a variable number of bits are translated.
We concatenate the effective address with the current PID value and the
Address Space value, and we use that virtual address, a variable number of
the upper address bits for the comparison. We check all of those bits with
the on-chip TLB entries. Then, in the case of a hit, we get the RPN as our
output. The number of bits that are translated depends on the size field of
the matching TLB entry.
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