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Relation of MMU and Other Caches
Mouse over the CPU diagram to learn more.
CPU
fetch
LSU
L2
Cache
MMU
IL1
DL1
• MMU stores address mappings in on-chip TLBs.
• TLBs are “caches” of effective to real mappings.
- May have a variety of cache structures (just for storing the mappings)
- Prepare for “L1 and L2 MMU” terminology
It is important to distinguish between what is happening in the MMU and the
L1 and L2 cache nomenclature.
You should remember that the MMU stores address mappings in on-chip
TLBs and that the TLBs are also caches. They do not contain instructions or
data, but they do contain mappings of effective address to real address.
The L1 and L2 MMUs are not the same as the L1 and the L2 caches. The L1
and L2 caches for instructions and data contain exactly that—instructions
and data. L1 and L2 MMUs are only relative; those levels are only related to
each other in terms of the way the MMU is structured for efficiency’s sake.
Move your mouse pointer over the CPU diagram for more information.
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