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Document type:
User's Manual (MUT)
3.5.
Title:
Mod. V1724 8 Channel 14bit - 100MS/s Digitizer
Revision date:
25/09/2009
Revision:
19
Trigger management
All the channels in a board share the same trigger: this means that all the channels store
an event at the same time and in the same way (same number of samples and same
position with respect to the trigger); several trigger sources are available.
Mother Board
Mezzanines
Memory
Buffers
TRG OUT
TRG IN
D
Q
Acquisition
Logic
TRIGGER
ADC
8
x8
SCLK
8
LOCAL TRG
Enable Mask
8
Digital
Thresholds
SW TRG
VME
Interface
Local Bus
Interface
Fig. 3.17: Block diagram of Trigger management
3.5.1.
External trigger
External trigger can be NIM/TTL signal on LEMO front panel connector, 50 Ohm
impedance. The external trigger is synchronised with the internal clock (see § 3.2.3); if
External trigger is not synchronised with the internal clock, a one clock period jitter
occurs.
3.5.2.
Software trigger
Software trigger are generated via VME bus (write access in the relevant register, see
§ 4.21).
3.5.3.
Local channel auto-trigger
Each channel can generate a local trigger as the digitised signal exceeds the Vth
threshold (ramping up or down, depending on VME settings), and remains under or over
threshold for Nth “quartets” of samples at least (Nth is programmable via VME). The Vth
digital threshold, the edge type, and the minimum number Nth of couples of samples are
programmable via VME register accesses, see § 4.3 and § 4.6; actually local trigger is
delayed of Nth quartets of samples with respect to the input signal.
NPO:
00103/05:V1724x.MUTx/19
Filename:
V1724_REV19.DOC
Number of pages:
74
Page:
38