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UM10116
NXP Semiconductors
P89LPC933/934/935/936 User manual
Table 107. Data EEPROM control register (DEECON address F1h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
EEIF
HVERR
ECTL1
ECTL0
-
-
-
EADR8
Reset
0
0
0
0
0
0
x
0
Table 108. Data EEPROM control register (DEECON address F1h) bit description
Bit Symbol
0
EADR8
1:3
Description
Most significant address (bit 8) of the Data EEPROM. EADR7-0 are in DEEADR.
Reserved.
5:4 ECTL1:0 Operation mode selection:
The following modes are selected by ECTL[1:0]:
00 — Byte read / write mode.
01 — Reserved.
10 — Row (64 bytes) fill.
11 — Block fill (512 bytes).
6
HVERR
High voltage error. Indicates a programming voltage error during program or
erase.
7
EEIF
Data EEPROM interrupt flag. Set when a read or write finishes, reset by software.
Byte Mode: In this mode data can be read and written to one byte at a time. Data is in the
DEEDAT register and the address is in the DEEADR register. Each write requires
approximately 4 ms to complete. Each read requires three machines after writing the
address to the DEEADR register.
Row Fill: In this mode the addressed row (64 bytes, with address DEEADR[5:0] ignored)
is filled with the DEEDAT pattern. To erase the entire row to 00h or program the entire row
to FFh, write 00h or FFh to DEEDAT prior to row fill. Each row fill requires approximately
4 ms to complete.
Block Fill: In this mode all 512 bytes are filled with the DEEDAT pattern. To erase the block
to 00h or program the block to FFh, write 00h or FFh to DEEDAT prior to the block fill.
Prior to using this command EADR8 must be set = 1. Each Block Fill requires
approximately 4 ms to complete.
In any mode, after the operation finishes, the hardware will set EEIF bit. An interrupt can
be enabled via the IEN1.7 bit. If IEN1.7 and the EA bits are set, it will generate an interrupt
request. The EEIF bit will need to be cleared by software.
18.1 Data EEPROM read
A byte can be read via polling or interrupt:
1. Write to DEECON with ECTL1/ECTL0 (DEECON[5:4]) = ‘00’ and correct bit 8 address
to EADR8. (Note that if the correct values are already written to DEECON, there is no
need to write to this register.)
2. Without writing to the DEEDAT register, write address bits 7 to 0 to DEEADR.
3. If both the EIEE (IEN1.7) bit and the EA (IEN0.7) bit are logic 1s, wait for the Data
EEPROM interrupt then read/poll the EEIF (DEECON.7) bit until it is set to logic 1. If
EIEE or EA is logic 0, the interrupt is disabled, only polling is enabled.
4. Read the Data EEPROM data from the DEEDAT SFR.
UM10116_3
User manual
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 10 February 2009
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