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UM10116
NXP Semiconductors
P89LPC933/934/935/936 User manual
Table 65. Serial Port Control register (SCON - address 98h)
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Table 66. Serial Port Control register (SCON - address 98h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .74
Table 67. Serial Port modes . . . . . . . . . . . . . . . . . . . . . .74
Table 68. Serial Port Status register (SSTAT - address BAh)
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Table 69. Serial Port Status register (SSTAT - address BAh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .75
Table 70. FE and RI when SM2= 1 in Modes 2 and 3 . . .78
Table 71. Slave 0/1 examples . . . . . . . . . . . . . . . . . . . . .81
Table 72. Slave 0/1/2 examples . . . . . . . . . . . . . . . . . . .81
Table 73. I2C data register (I2DAT - address DAh) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Table 74. I2C slave address register (I2ADR - address DBh)
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Table 75. I2C slave address register (I2ADR - address DBh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .83
Table 76. I2C Control register (I2CON - address D8h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Table 77. I2C Control register (I2CON - address D8h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Table 78. I2C Status register (I2STAT - address D9h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Table 79. I2C Status register (I2STAT - address D9h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Table 80. I2C clock rates selection . . . . . . . . . . . . . . . . .86
Table 81. I2C Control register (I2CON - address D8h) . .86
Table 82. I2C Control register (I2CON - address D8h) . .88
Table 83. Master Transmitter mode . . . . . . . . . . . . . . . . .91
Table 84. Master Receiver mode . . . . . . . . . . . . . . . . . .92
Table 85. Slave Receiver mode . . . . . . . . . . . . . . . . . . .93
Table 86. Slave Transmitter mode . . . . . . . . . . . . . . . . . .95
Table 87. SPI Control register (SPCTL - address E2h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Table 88. SPI Control register (SPCTL - address E2h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Table 89. SPI Status register (SPSTAT - address E1h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Table 90. SPI Status register (SPSTAT - address E1h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Table 91. SPI Data register (SPDAT - address E3h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Table 92. SPI master and slave selection . . . . . . . . . . .100
Table 93. Comparator Control register (CMP1 - address
ACh, CMP2 - address ADh) bit allocation . . .107
Table 94. Comparator Control register (CMP1 - address
ACh, CMP2 - address ADh) bit description . .107
Table 95. Keypad Pattern register (KBPATN - address 93h)
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 96. Keypad Pattern register (KBPATN - address 93h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 97. Keypad Control register (KBCON - address 94h)
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 98. Keypad Control register (KBCON - address 94h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 99. Keypad Interrupt Mask register (KBMASK address 86h) bit allocation . . . . . . . . . . . . . . . 111
Table 100.Keypad Interrupt Mask register (KBMASK address 86h) bit description . . . . . . . . . . . . . 111
Table 101.Watchdog timer configuration . . . . . . . . . . . . 112
Table 102.Watchdog Timer Control register (WDCON address A7h) bit allocation . . . . . . . . . . . . . . 114
Table 103.Watchdog Timer Control register (WDCON address A7h) bit description . . . . . . . . . . . . . 114
Table 104.Watchdog timeout vales . . . . . . . . . . . . . . . . 114
Table 105.AUXR1 register (address A2h) bit allocation 117
Table 106.AUXR1 register (address A2h) bit description 117
Table 107.Data EEPROM control register (DEECON
address F1h) bit allocation. . . . . . . . . . . . . . . 119
Table 108.Data EEPROM control register (DEECON
address F1h) bit description. . . . . . . . . . . . . . 119
Table 109.Flash Memory Control register (FMCON - address
E4h) bit allocation . . . . . . . . . . . . . . . . . . . . . 124
Table 110. Flash Memory Control register (FMCON - address
E4h) bit description . . . . . . . . . . . . . . . . . . . . 124
Table 111. Boot loader address and default Boot vector 127
Table 112. In-system Programming (ISP) hex record
formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 113. IAP error status . . . . . . . . . . . . . . . . . . . . . . . 133
Table 114. IAP function calls . . . . . . . . . . . . . . . . . . . . . 134
Table 115. Flash User Configuration Byte (UCFG1) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 116. Flash User Configuration Byte (UCFG1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 117. Oscillator type selection . . . . . . . . . . . . . . . . 137
Table 118. Sector Security Bytes (SECx) bit allocation . 137
Table 119. Sector Security Bytes (SECx) bit description 137
Table 120.Effects of Security Bits . . . . . . . . . . . . . . . . . 138
Table 121.Boot Vector (BOOTVEC) bit allocation . . . . . 138
Table 122.Boot Vector (BOOTVEC) bit description . . . . 138
Table 123.Boot Status (BOOTSTAT) bit allocation . . . . 138
Table 124.Boot Status (BOOTSTAT) bit description . . . 138
Table 125.Instruction set summary . . . . . . . . . . . . . . . . 140
UM10116_3
User manual
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 10 February 2009
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