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Chapter 4: User Peripherals
clock pin to the output of a second timer block, making it possible to cascade the timers to build more complex
timer arrays. Each timer counter is controlled by eight registers, which allow it to be configured for input capture
and output waveform generation.
Each timer has a regular programmer’s
interface that allows easy configuration
of each operating mode.
The timer block is a 16 bit counter with an 8 bit prescaler that is managed by two control registers.
The timer control registers configure the prescaler CC0-CC7 and the various capture compare
operating modes.
The clock source is selected with the ECKEN bit in control register 1. By default this bit is set at zero to select
PCLK. The timer prescaler value is held in the lower eight bits of control register 2. This prescaler is only applied
to the system clock, an external clock source is fed directly to the timer. If the external clock is used an additional
bit EXEDG in control register 1 allows you to determine if the rising or falling edge will increment the counter.
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