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User’s Manual
R7S72100 CPU (GENMAI) Optional Board
32
RTK7721000B00000BR
User's Manual
Renesas Microcomputer
RZ/A Series
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corporation without notice. Please review the latest information published by
Renesas Electronics Corporation through various means, including the Renesas Electronics
Corporation website (http://www.renesas.com).
www.renesas.com
Rev.0.05
2013.9
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you
or third parties arising from the use of these circuits, software, or information.
2.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics
does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
3.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of
third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No
license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of
Renesas Electronics or others.
4.
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Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration,
modification, copy or otherwise misappropriation of Renesas Electronics product.
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recommended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below.
“Standard”:
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equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc.
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Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to
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Electronics.
6.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or
damages arising out of the use of Renesas Electronics products beyond such specified ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have
specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,
Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to
guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas
Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation
of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by
you.
8.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility
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(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries.
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(2012.4)
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Renesas development tools and products are directly covered by the European Union's Waste
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As a result, this equipment, including all accessories, must not be disposed of as household
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About This Manual
1. Purpose and Target Readers
This manual is designed to provide the user with an understanding of the functions and operating specifications of this
extension board. A basic knowledge of electrical circuits, logical circuits, and microcomputers (MCUs) is necessary in
order to use this manual.
This manual is composed of an overview of the optional board; its functional and operational specifications.
Carefully read all notes described in the body of text in the manual.
The Revision History summarizes the modifications and additions to the previous versions. Refer to the text of the manual
for details.
The following document applies to the R7S72100 CPU optional board RTK7721000B00000BR.
Document Type
User's Manual
Description
Document Title
Describes functional specifications
R7S72100 CPU optional
(devices, memory maps, electrical
board
characteristics), and operational
RTK7721000B00000BR
specifications (connectors, and
User's Manual
Document No.
This publication
switches)
The following documents apply to the RZ/A1H group. Make sure to refer to the latest version of these documents which
can be obtained from Renesas Electronics website.
Document Type
Description
Application note
Applications, sample programs, etc.
RENESAS TECHNICAL
Information regarding product
UPDATE
specifications, documents, etc.
Document Title
Document No.
Available on Renesas Electronics website
2. Frequently Used Abbreviations and Acronyms
ACIA
Asynchronous Communication Interface Adapter
bps
Bits per second
CRC
Cyclic Redundancy Check
DMA
Direct Memory Access
DMAC
Direct Memory Access Controller
GSM
Global System for Mobile Communications
Hi-Z
High Impedance
IEBus
Inter Equipment bus
I/O
Input/Output
IrDA
Infrared Data Association
LSB
Least Significant Bit
MSB
Most Significant Bit
NC
Non-Connection
PLL
Phase Locked Loop
PWM
Pulse Width Modulation
SFR
Special Function Registers
SIM
Subscriber Identity Module
UART
Universal Asynchronous Receiver/Transmitter
VCO
Voltage Controlled Oscillator
All trademarks and registered trademarks are the property of their respective owners.
Table of Contents
1.
2.
3.
Overview.................................................................................................................................................... 1-1
1.1
Overview .......................................................................................................................................... 1-1
1.2
System Configuration using RTK7721000B00000BR ..................................................................... 1-2
1.3
External Specifications..................................................................................................................... 1-3
1.4
Exterior Appearance ........................................................................................................................ 1-4
1.5
Block Diagram .................................................................................................................................. 1-5
1.6
Parts Layout ..................................................................................................................................... 1-6
1.7
Absolute Maximum Ratings ............................................................................................................. 1-9
1.8
Operating Conditions........................................................................................................................ 1-9
Functional Specification............................................................................................................................. 2-1
2.1
Functions Overview.......................................................................................................................... 2-1
2.2
CPU.................................................................................................................................................. 2-2
2.2.1
R7S72100 Overview ................................................................................................................ 2-2
2.2.2
RTK7721000B00000BR Pin Functions ................................................................................... 2-2
2.2.3
RTK7721000B00000BR Module Applicability ....................................................................... 2-16
2.3
IEBus Interface............................................................................................................................... 2-17
2.4
LIN Interface................................................................................................................................... 2-18
2.5
SIM Card Interface ......................................................................................................................... 2-19
2.6
IrDA Module ................................................................................................................................... 2-20
2.7
UART Interface............................................................................................................................... 2-21
2.8
Audio Interface ............................................................................................................................... 2-22
2.9
CD Deck Interface .......................................................................................................................... 2-23
2.10
HCI Module Interface ..................................................................................................................... 2-25
2.11
LCD Panel Output Interface ........................................................................................................... 2-26
2.12
Analog RGB Output Interface ........................................................................................................ 2-29
2.13
Digital Video Signal Input Interface ................................................................................................ 2-32
2.14
CMOS Camera Input Interface....................................................................................................... 2-33
2.15
Key Input Switch............................................................................................................................. 2-34
2.16
Power Configuration....................................................................................................................... 2-35
Operational Specification........................................................................................................................... 3-1
3.1
Connector Overview......................................................................................................................... 3-1
3.1.1
Expansion Connectors (CN1 to CN9) ...................................................................................... 3-3
3.1.2
SIM Card Slot (J2).................................................................................................................. 3-10
3.1.3
UART Connector (J3)............................................................................................................. 3-11
3.1.4
IEBus Connector (J4)............................................................................................................. 3-12
3.1.5
LIN Connector (J5)................................................................................................................. 3-13
3.1.6
Lineout Pin Jacks (J6 and J9)................................................................................................ 3-14
3.1.7
HCI Connector (J7) ................................................................................................................ 3-15
3.1.8
CD Deck Connector (J8)........................................................................................................ 3-16
3.1.9
LCD Panel Connectors (J10 to J14) ...................................................................................... 3-17
3.1.10
Analog RGB Output Connectors (J15 and J16)..................................................................... 3-24
3.1.11
CMOS Camera Connector (J17)............................................................................................ 3-26
3.1.12
Digital Video Signal Input Connectors (J18 and J19) ............................................................ 3-28
3.2
Operation Parts Layout .................................................................................................................. 3-31
3.2.1
Jumpers (JP1 to JP7)............................................................................................................. 3-33
3.2.2
Switches................................................................................................................................. 3-35
3.3
Dimensions..................................................................................................................................... 3-37
Appendix RTK7721000B00000BR Schematics ...................................................................................................1
R7S72100 CPU (GENMAI) Optional Board RTK7721000B00000BR
1.
Overview
1.1
Overview
1. Overview
RTK7721000B00000BR is an optional board for the R7S72100 CPU board. The R7S72100 functions and its performance
evaluation and the application software preceding development and evaluation can be executed by using the R7S72100 CPU
board RTK7721000B00000BR. The features of the RTK7721000B00000BR are described below.
• Includes the following connectors to connect the TFT-LCD panel.
•
•
•
•
•
Alpha Project LCD-KIT-B01: 2
Renesas R0P7724LE0011RL: 1
General MIL connector: 40-pin×2
Includes a video DAC and converts the TFT-LCD panel control signal to the analog RGB. The evaluation for the
VDC5 display function can be executed by connecting to the monitor for PC.
Includes general MIL connectors to evaluate the digital video signal input function (40-pin×1, 20-pin×1).
Includes a 26-pin MIL connector to connect Aptina CMOS camera (MT9V024IA7XTCD ES)
Includes audio DAC, CD deck interface, and key input switch which enable the preceding development for audio
system.
Includes UART connector, IrDA module, SIM card slot, LIN connector, and IEBus connector as the R7S72100
peripheral function interface.
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Rev.0.05
1-1
R7S72100 CPU (GENMAI) Optional Board RTK7721000B00000BR
1.2
1. Overview
System Configuration using RTK7721000B00000BR
Figure 1.2.1 shows the System Configuration using RTK7721000B00000BR.
Figure 1.2.1
System Configuration using RTK7721000B00000BR
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Sep. 06, 2013
Rev.0.05
1-2
R7S72100 CPU (GENMAI) Optional Board RTK7721000B00000BR
1.3
1. Overview
External Specifications
Table 1.3.1 lists the RTK7721000B00000BR External Specifications.
Table 1.3.1
RTK7721000B00000BR External Specifications
No.
1
Item
TFT-LCD panel output
Description
Includes three types of TFT-LCD panel connectors.
• Alpha Project LCD-KIT-B01: 2
• Renesas R0P7724LE0011RL: 1
• General MIL standard connector: 40-pin×2
2
Analog RGB output
Converts digital RGB for TFT-LCD to analog RGB using Analog Devices video DAC
(ADV7123).
• Analog RGB connector: D-sub 15-pin connector×2
3
Digital video signal input
4
connectors
5
Switches
6
Board specification
R20UT2696EJ0005
Sep. 06, 2013
Includes digital video signal input connector for R7S72100 VDC5.
•
•
•
•
•
•
•
•
•
•
•
Rev.0.05
•
•
•
•
General MIL connector: 40-pin×1, 20-pin×1
Lineout pin jacks (3.5 φ): 2
SIM card slot
UART connector
LIN connector
IEBus connector
CD deck connector
HCI module connector
CMOS camera connector
DIP switch for video DAC setting: 8/package×1
DIP switch for key input: push switch×12, 4-directional switch with a center
push type×1
Dimensions: 175×230mm
Mounting form: 6 layered, double-sided
Board thickness: 1.6mm
Number of board: 1
1-3
R7S72100 CPU (GENMAI) Optional Board RTK7721000B00000BR
1.4
1. Overview
Exterior Appearance
Figure1.4.1 shows the RTK7721000B00000BR Exterior Appearance.
Figure1.4.1
RTK7721000B00000BR Exterior Appearance
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Rev.0.05
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R7S72100 CPU (GENMAI) Optional Board RTK7721000B00000BR
1.5
1. Overview
Block Diagram
Figure1.5.1 shows the RTK7721000B00000BR Block Diagram.
ICE
Key Input
(4×3)
UDI
75
DVDEC
RCA×
RCA 2
VIN2
ADC
Joystick
R7S72100
(324BGA)
RESET
NMI
IRQ6
RJ-45
Pin Header
(3pin)
100
PHY
uPD60610
INTC
MII:8
CAN
Transceiver
100
LVDS
ETHER
RSCAN
Pin Header
(4pin)
IEBus
Transceiver
IEBB
Pin Header
(3pin)
LIN
Transceiver
RLIN3
VDC5
LVDS
Output
D/A Conv.
ADV7123
Dsub-15
D/A Conv.
ADV7123
Dsub-15
24
LCD Output
(ch1)
8
DV Input
(ch1)
20pin MIL
24
LCD Output
(ch0)
24
DV Input
(ch0)
40pin MIL
16
CMOS Input
MIC
USB×2
90
SSIF0
USB
Audio
Codec
(WM8978)
HP
SD Card
Slot
4
ch0
RSPI4
RSPI
SSL is controlled by port.
SSIF1
CD Deck
SDHI
MMC Card
Slot
4
MOST I/F
Board
SSIF
ch1
MMC
8
MLB
SSIF3
DAC
(AK4353)
SPK
SSIF4
DAC
(AK4353)
SPK
ch2
ch2
SSIF5
TOSLINK
(TODX)
RSPDIF
EEPROM
(16KB)
NAND
(512MB)
ch0
RIIC
ch2
8
HCI
SCIF7
SCIF2
Tx, Rx
RS-232C
Transceiver
Dsub-9
SCIF
FLCTL
RL78/G1C-S
Serial Flash
(64MB×2)
Serial Flash
(64MB)
8
4
USB
Mini-B
SPIBSC
SPIBSC
SCI
BSC
SCIF3
SCI0
TxD, RxD, SCK
16bit
CS0
NOR
(64MB)
CS1
NOR
(64MB)
CS2
SDRAM
(64MB)
CS3
SDRAM
(64MB)
UART
TxD, RxD
IrDA
Module
TxD, RxD, SCK
SIM Card
Slot
*Memory capacity uint : Byte
External
Connector
CPU board
Figure1.5.1
Bootable
Optional
Dedicated
connector
Expansion
connector
RTK7721000B00000BR Block Diagram
R20UT2696EJ0005
Sep. 06, 2013
Optional
Board
Rev.0.05
1-5
Figure1.6.1
R20UT2696EJ0005
Sep. 06, 2013
Rev.0.05
U3: IrDA module
J15: Analog RGB connector
J3: UART connector
J2: SIM card slot
CN4: Expansion connector
J8: CD deck connector
CN2: Expansion connector
CN9: Expansion connector
U4: IEBus transceiver
J4: IEBus connector
J14: LCD panel connector
(ch1, R0P7724LE0011RL)
SW1 to SW13: Key input switches
CN5: Expansion connector
U8: Video DAC
CN6: Expansion connector
J9: Lineout pin jack
U7: Audio DAC
U6: Audio DAC
J6: Lineout pin jack
CN7: Expansion connector
CN8: Expansion connector
U5: LIN transceiver
J5: LIN connector
SW14:
DIP switch for video DAC setting
1.6
U10: Video DAC
J16: Analog RGB connector
R7S72100 CPU (GENMAI) Optional Board RTK7721000B00000BR
1. Overview
Parts Layout
Figure1.6.1 and Figure1.6.2 show the Parts Layout of the RTK7721000B00000BR.
RTK7721000B00000BR Parts Layout (Top View of Component Side)
1-6
R7S72100 CPU (GENMAI) Optional Board RTK7721000B00000BR
Figure1.6.2
RTK7721000B00000BR Parts Layout (Top View of Solder Side)
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Sep. 06, 2013
1. Overview
Rev.0.05
1-7
R7S72100 CPU (GENMAI) Optional Board RTK7721000B00000BR
1. Overview
Table1.6.1 and Table1.6.2 list the main Parts of the RTK7721000B00000BR.
Table1.6.1
RTK7721000B00000BR Main Parts (1) IC
Part Number
Part Name
Type (Manufacturer)
U1
8V regulator
LM20242 (TI)
U3
IrDA module
RPM871 (ROHM)
U4
U5
IEBus transceiver
LIN transceiver
R2A11210SP (Renesas)
U6, U7
Audio DAC
AK4353VF (AKM)
U8, U10
Video DAC
ADV7123 (Analog Devidces)
CMOS camera oscillator
SG8002CA_27MHz (Epson)
X2
Table1.6.2
Recommended Optional Parts
12V → 8V
MAX13020 (Maxim)
RTK7721000B00000BR Main Parts (2) Connectors
Part Number
CN2
Expansion connector (30-pin)
Part Name
HIF3FB-30DA-2.54DSA (HRS)
Type (Manufacturer)
CN4, CN5,
Expansion connector (20-pin)
HIF3FB-20DA-2.54DSA (HRS)
CN6, CN9
Expansion connector (30-pin)
SSW-115-01-L-D (Samtec)
CN7
Expansion connector (34-pin)
SSW-117-01-L-D (Samtec)
J2
SIM card slot
FMS006Z-2001-1 (Yamaichi)
J3
UART connector
S5B-XH-A (JST)
J4
IEBus connector
S4B-XH-A (JST)
J5
LIN connector
S3B-XH-A (JST)
J6, J9
Lineout pin jack
HSJ1456-010320 (Hoshiden)
J7
HCI connector
HIF3FC-20PA-2.54DSA (HRS)
Recommended Optional Parts
CN8
J8
CD deck connector
IMSA-9617S-22Y922 (IRISO)
J10, J12
LCD-KIT-B01 connector
XF2J-4024-12A (OMRON)
J11, J13
General LCD connector
HIF3FC-40PA-2.54DSA (HRS)
J14
R0P7724LE0011RL connector
8611-060S (KEL)
J15, J16
Analog RGB output connector
XM4L-1542-132 (OMRON)
J17
CMOS camera connector
N2526-6002RB (3M)
J18
Digital video signal input connector HIF3FC-40PA-2.54DSA (HRS)
For ch1
For ch0
(40-pin)
J19
Digital video signal input connector HIF3FC-20PA-2.54DSA (HRS)
For ch1
(20-pin)
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R7S72100 CPU (GENMAI) Optional Board RTK7721000B00000BR
1.7
1. Overview
Absolute Maximum Ratings
Table1.7.1 lists the RTK7721000B00000BR Absolute Maximum Ratings.
Table1.7.1
RTK7721000B00000BR Absolute Maximum Ratings
Symbol
12Vcc
*1
Item
Value
Remarks
12V system power supply voltage
-0.3V to 15V
Vss reference
5Vcc *1
5V system power supply voltage
-0.3V to 6.25V
Vss reference
3Vcc *1
3.3V system power supply voltage
-0.3V to 4.6V
Vss reference
AVcc *1
Analog 3.3V system power supply
-0.3V to 4.6V
AVss reference
voltage
Topr
Operating ambient temperature *2
Tstg
Storage ambient temperature *2
0°C to 50°C
Do not expose to condensation or corrosive gases.
-10°C to 60°C
Do not expose to condensation or corrosive gases.
[Note] *1 Supplied from R7S72100 CPU board.
*2 The ambient temperature is the air temperature immediate to the board.
1.8
Operating Conditions
Table1.8.1 lists the RTK7721000B00000BR Operating Conditions.
Table1.8.1
RTK7721000B00000BR Operating Conditions
Symbol
Item
Value
Remarks
12Vcc *1
12V system power supply voltage
10.8V to 13.2V
Vss reference
5Vcc *1
5V system power supply voltage
4.5V to 5.5V
Vss reference
*1
3.3V system power supply voltage
3.0V to 3.6V
Vss reference
AVcc *1
Analog 3.3V system power supply
3.0V to 3.6V
Vss reference
-
Maximum consumption voltage
3Vcc
voltage
Topr
Operating ambient temperature
Up to 3A
*2
0°C to 40°C
Includes R7S72100 CPU board consumption current
Do not expose to condensation or corrosive gases.
[Note] *1 Supplied from R7S72100 CPU board.
*2 The ambient temperature is the air temperature immediate to the board.
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Rev.0.05
1-9
R7S72100 CPU (GENMAI) Optional Board RTK7721000B00000BR
R20UT2696EJ0005
Sep. 06, 2013
Rev.0.05
1. Overview
1-10
R7S72100 CPU (GENMAI) Optional Board
2.
Functional Specification
2.1
Functions Overview
RTK7721000B00000BR
2.
Functional Specification
Table2.1.1 lists the RTK7721000B00000BR Function Modules.
Table2.1.1
RTK7721000B00000BR Function Modules
Section
Function
2.2
CPU
2.3
IEBus Interface
2.4
LIN Interface
2.5
SIM Card Interface
2.6
IrDA Module
Description
• R7S72100 pin functions used on RTK7721000B00000BR
• Connect the R7S72100 IEBus controller (IEBB) and the
IEBus driver.
• Connect the R7S72100 LIN/UART interface (RLIN3) and the LIN
driver.
• Connect the R7S72100 serial communication interface (SCI)
and the SIM card slot.
• Connect the R7S72100 serial communication interface (SCI) and
the IrDA module.
UART Interface
• Connect the R7S72100 serial communication interface (SCI) pin to
2.8
Audio Interface
• Connect the R7S72100 and the D/A converter.
2.9
CD Deck Interface
2.10
HCI Module Interface
2.11
LCD Panel Output Interface
• Connect the R7S72100 Renesas serial peripheral interface
(RSPI) and serial sound interface (SSIF) and the CD deck.
• Connect the pins for the R7S72100 HCI module to the MIL
connector.
• Include 5 connectors with 3 types for LDC panel connectors.
2.7
the UART connector.
- Two 96KHz, 24-bit D/A converters are included.
- Alpha Project LCD-KIT-B01 connector (ch0 and ch1)
- Renesas R0P7724LE0011RL connector (ch1 only)
- General MIL standard connector (ch0 and ch1)
2.12
Analog RGB Output Interface
• Convert the digital RGB for LCD to analog RGB using
Analog Devices video DAC (ADV7123)
Digital Video Signal Input Interface
• Include the digital video signal input connector for the
R7S72100 VDC5.
- Analog RGB connectors: D-sub 15-pin connector×2
2.13
- General digital video signal input connector: Digital video signal
input connector: 20/40-pin MIL standard connector
2.14
CMOS Camera Input Interface
• Connect the R7S72100 capture engine unit (CEU) and the
CMOS camera input connector.
- Aptina CMOS camera (MT9V024IA7XTCD ES) connector×1
2.15
Key Input
2.16
Power Configuration
Operation specifications
-
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
• Connect the R7S72100 A/D converter (ADC) and the
switches.
• Power configuration of the RTK7721000B00000BR
• Connectors, switches
(described in Chapter 3)
2-1
R7S72100 CPU (GENMAI) Optional Board
2.2
RTK7721000B00000BR
2.
Functional Specification
CPU
2.2.1
R7S72100 Overview
The RTK7721000B00000BR is used by connecting with the R7S72100 CPU board RTK772100BC00000BR which has the
32-bit RISK microcomputer with the maximum CPU clock frequency 400MHx.
2.2.2
RTK7721000B00000BR Pin Functions
Table 2.2.1to Table 2.2.14 show the RTK7721000B00000BR Pin Functions.
Table 2.2.1
Pin
No.
RTK7721000B00000BR Pin Functions (1)
Pin Name
A1
Vss
A2
P6_4 / D4 / LCD1_DATA12 /
Function
D4
Description
Expansion
Connector
Data bus
CN1-15
Connected to DIPSW as a clock selection
-
Remarks
CRx2 / IRQ3 / RTS5 / RSPCK1 /
DV0_DATA20
A3
P0_3 / MD_CLKS
MD_CLKS
SW1-5
input.
A4
A5
P11_0 / DV0_DATA12 / TIOC4A /
DV0_DATA12
Connected to DV0 input connector
SCK6 / LCD0_DATA7 / VIO_D12
LCD0_DATA7
Connected to LCD0 output connector
VIO_D12
Connected to CMOS camera input connector
P9_6 / LCD1_DATA22 /
SPBIO20_0
Connected to serial flash memory 1
SPBIO20_0 / SSIWS2 / RTS1 /
LCD1_DATA22
Connected to LCD1 output connector
P9_3 / LCD1_DATA19 /
SPBSSL_0
Connected to serial flash memory 1 and 2
SPBSSL_0 / TxD1
LCD1_DATA19
Connected to LCD1 output connector
P5_9 / WE2/DQMUL / ET_MDC /
ET_MDC
Connected to Ethernet PHY
CN9-28
CN9-24
CS5
A6
A7
CN9-19
CN9-16
DV0_VSYNC / IRQ2 / CRx1 /
IERxD / LCD1_DATA16
JP7:Short
JP7:Open
JP4:2-3
JP7:Open
CRx1
Connected to CAN transceiver
JP4:1-2
IERxD
Connected to IEBus transceiver
JP4:Open
JP2:1-2
JP7:Short
LCD1_DATA16
Connected to LCD1 output connector
JP4:Open
JP2:Open
JP7:Short
A8
Vss
A9
P5_6 / TXOUT0P /
TXOUT0P
Connected to LCD panel for LVDS
-
LCD1_DATA6 / LCD0_DATA22 /
LCD1_DATA6
Connected to LCD1 output connector
CN9-8
DV1_DATA6 / TxD6 / IRQ6 /
DV1_DATA6
Connected to DV1 input connector
SPDIF_IN / DV0_DATA14
A10
P5_2 / TXOUT2P /
TXOUT2P
Connected to LCD panel for LVDS
-
LCD1_DATA2 / LCD0_DATA18 /
LCD1_DATA2
Connected to LCD1 output connector
CN9-4
DV1_DATA2 / SCK3 / TIOC1B /
DV1_DATA2
Connected to DV1 input connector
MOSI3
A11
P5_0 / TXCLKOUTP /
TXCLKOUTP
Connected to LCD panel for LVDS
-
LCD1_DATA0 / LCD0_DATA16 /
LCD1_DATA0
Connected to LCD1 output connector
CN9-2
DV1_DATA0 / TxD4 / TIOC0A /
DV1_DATA0
Connected to DV1 input connector
RSPCK3
A12
Vss
A13
VIN2B
Composite video, blanking, and sync (CVBS)
-
channel 1 input pin2
A14
VDAVss
: 3.3V system power supply,
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
: 1.18V system power supply,
: GND, Letters in Red indicate CPU board setting.
2-2
R7S72100 CPU (GENMAI) Optional Board
Table 2.2.2
Pin
No.
A15
RTK7721000B00000BR
2.
Functional Specification
RTK7721000B00000BR Pin Functions (2)
Pin Name
Function
VIN2A
Description
Composite video, blanking, and sync (CVBS)
Expansion
Connector
Remarks
-
channel 0 input pin2
A16
P0_2 / MD_CLK
MD_CLK
Connected to DIPSW as a clock mode input
-
A17
P1_6 / SCL3 / DV1_VSYNC /
SCL3
Connected to LCD1 output connector
CN8-20
IERxD / IRQ6 / VIO_D12 /
DV1_VSYNC
Connected to DV1 input connector
SDA1
Connected to TH7 of CPU board
CN8-15
SCL0
Connected to HCI connectoro
CN8-14
SW1-4
DV0_DATA12
A18
P1_3 / SDA1 / DV0_DATA19 /
ET_COL / IRQ3 / ADTRG
A19
P1_0 / SCL0 / DV0_DATA16 /
TCLKA / IRQ0 / VIO_VD /
Connected to LCD0 output connector
DV0_VSYNC
A20
Connected to CMOS camera input connector
P2_13 / D29 / SSL00 /
SPBIO11_0
Connected to serial flash memory 2
DV0_DATA13 / SPBIO11_0 /
LCD1_DATA13
Connected to LCD1 output connector
CN8-7
CTx3 / SCK0 / LCD1_DATA13 /
IRQ7
A21
P2_12 / D28 / RSPCK0 /
SPBIO01_0
Connected to serial flash memory 2
DV0_DATA12 / SPBIO01_0 /
LCD1_DATA12
Connected to LCD1 output connector
D0
Data bus
CN1-20
DV0_DATA14
Connected to DV0 input connector
CN9-30
LCD0_DATA5
Connected to LCD0 output connector
VIO_D14
Connected to CMOS camera input connector
CN8-8
CRx3 / IRQ6 / LCD1_DATA12 /
TIOC1B
A22
Vss
B1
Vcc
B2
Vss
B3
P6_0 / D0 / LCD1_DATA8 /
LRXD0 / DV0_CLK / TIOC1A /
IRQ5 / RxD3 / DV0_DATA16
B4
P11_2 / DV0_DATA14 / TIOC4C /
RxD6 / LCD0_DATA5 / VIO_D14
B5
P9_7 / LCD1_DATA23 /
SPBIO30_0
Connected to serial flash memory 1
SPBIO30_0 / SSIDATA2 /
LCD1_DATA23
Connected to LCD1 output connector
CN9-23
TIOC1A
B6
B7
B8
B9
P9_4 / LCD1_DATA20 /
SPBIO00_0
Connected to serial flash memory 1
SPBIO00_0 / RxD1
LCD1_DATA20
Connected to LCD1 output connector
P5_10 / WE3/DQMUU/AH /
P5_10
Connected to TH3
DV0_HSYNC / CTx1 / IETxD /
CTx1
Connected to CAN transceiver
LCD1_DATA17
IETxD
Connected to IEBus transceiver
CN9-22
CN9-15
LCD1_DATA17
Connected to LCD1 output connector
P5_8 / LCD0_EXTCLK / IRQ0 /
CS2
Connected to CS pin of SDRAM2
DV1_CLK / DV0_CLK / CS2
LCD0_EXTCLK
Connects external clock for LCD panel
P5_7 / TXOUT0M /
TXOUT0M
Connected to LCD panel for LVDS
CN9-7
LCD1_DATA7 / LCD0_DATA23 /
LCD1_DATA7
Connected to LCD1 output connector
DV1_DATA7 / RxD6 / TIOC0D /
DV1_DATA7
Connected to DV1 input connector
CN9-11
X1 (optional)
SPDIF_OUT / DV0_DATA15
B10
P5_3 / TXOUT2M /
TXOUT2M
Connected to LCD panel for LVDS
-
LCD1_DATA3 / LCD0_DATA19 /
LCD1_DATA3
Connected to LCD1 output connector
CN9-3
DV1_DATA3 / TxD3 / TIOC3C /
DV1_DATA3
Connected to DV1 input connector
MISO3
B11
P5_1 / TXCLKOUTM /
TXCLKOUTM
Connected to LCD panel for LVDS
-
LCD1_DATA1 / LCD0_DATA17 /
LCD1_DATA1
Connected to LCD1 output connector
CN9-1
DV1_DATA1 / RxD4 / TIOC0B /
DV1_DATA1
Connected to DV1 input connector
SSL30
B12
Vss
: 3.3V system power supply,
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
: 1.18V system power supply,
: GND, Letters in Red indicate CPU board setting.
2-3
R7S72100 CPU (GENMAI) Optional Board
Table 2.2.3
Pin
No.
B13
RTK7721000B00000BR
2.
Functional Specification
RTK7721000B00000BR Pin Functions (3)
Pin Name
Function
VIN1B
Description
Composite video, blanking, and sync (CVBS)
Expansion
Connector
Remarks
-
channel 1 input pin 1
B14
VDAVcc
B15
VIN1A
Composite video, blanking, and sync (CVBS)
-
channel 0 input pin 1
B16
P1_7 / SDA3 / DV1_HSYNC /
SDA3
Connected to LCD1 output connector
LRXD0 / IRQ7 / VIO_D13 /
DV1_HSYNC
Connected to DV1 input connector
SCL2
Connected to EEPROM
CN8-19
DV0_DATA13
B17
P1_4 / SCL2 / DV0_CLK / CRx1 /
IRQ4 / CAN_CLK
CN8-18
Connected to MOST I/F connector
Connected to DAC (AK4353) 1 and 2
B18
B19
P1_2 / SCL1 / DV0_DATA18 /
SCL1
Connected to TH6
FRB / IRQ2 / LCD1_EXTCLK
FRB
Connected to NAND flash memory
P2_15 / D31 / MISO0 /
SPBIO31_0
Connected to serial flash memory 2
DV0_DATA15 / SPBIO31_0 /
LCD1_DATA15
Connected to LCD1 output connector
CN8-16
CN8-9
CAN_CLK / RxD0 /
LCD1_DATA15 / IRQ1
B20
PVcc
B21
Vss
B22
P2_10 / D26 / ET_RXD2 /
ET_RXD2
Connected to Ethernet PHY
-
SW2-1:ON
DV0_DATA10 / SSIRxD0 /
LTXD0
Connected to LIN connector
CN7-34
SW2-1:OFF
LTXD0 / LCD1_DATA10 /
LCD1_DATA10
Connected to LCD1 output connector
D5
Data bus
CN1-14
D2
Data bus
CN1-18
P11_3 / DV0_DATA15 / TIOC4D /
DV0_DATA15
Connected to DV0 input connector
CN9-29
LCD0_DATA4 / VIO_D15
LCD0_DATA4
Connected to LCD0 output connector
VIO_D15
Connected to CMOS camera input connector
P11_1 / DV0_DATA13 / TIOC4B /
DV0_DATA13
Connected to DV0 input connector
TxD6 / LCD0_DATA6 / VIO_D13
LCD0_DATA6
Connected to LCD0 output connector
VIO_D10/MOSI4
C1
P6_5 / D5 / LCD1_DATA13 /
CTx2 / SCK5 / SSL10 /
DV0_DATA21
C2
Vcc
C3
Vss
C4
P6_2 / D2 / LCD1_DATA10 /
LRXD1 / IRQ7 / TCLKA /
TIOC2A / RxD2 / DV0_DATA18
C5
C6
C7
VIO_D13
Connected to CMOS camera input connector
P9_5 / LCD1_DATA21 /
SPBIO10_0
Connected to serial flash memory 1
SPBIO10_0 / SSISCK2 / CTS1 /
LCD1_DATA21
Connected to LCD1 output connector
P9_2 / LCD1_DATA18 /
SPBCLK_0
Connected to serial flash memory 1 and 2
SPBCLK_0 / LTXD0 / SCK1 / A0
LCD1_DATA18
Connected to LCD1 output connector
CN9-27
CN9-21
CS4
C8
CN9-20
JP6:Short
C9
Vss
C10
P5_5 / TXOUT1M /
TXOUT1M
Connected to LCD panel for LVDS
-
LCD1_DATA5 / LCD0_DATA21 /
FCE
Connected to NAND flash memory
CN9-5
C11
JP6:Open
DV1_DATA5 / AUDIO_XOUT /
LCD1_DATA5
Connected to LCD1 output connector
TIOC0C / FCE / DV0_DATA13
DV1_DATA5
Connected to DV1 input connector
P5_4 / TXOUT1P /
TXOUT1P
Connected to LCD panel for LVDS
-
LCD1_DATA4 / LCD0_DATA20 /
LCD1_DATA4
Connected to LCD1 output connector
CN9-6
DV1_DATA4 / RxD3 / TIOC3D /
DV1_DATA4
Connected to DV1 input connector
R110: mounted
DV0_DATA12
C12
LVDSAPVcc
: 3.3V system power supply,
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
: 1.18V system power supply,
: GND, Letters in Red indicate CPU board setting.
2-4
R7S72100 CPU (GENMAI) Optional Board
Table 2.2.4
Pin
No.
C13
RTK7721000B00000BR
2.
Functional Specification
RTK7721000B00000BR Pin Functions (4)
Pin Name
Function
VRM
Description
A/D converter BOTTOM reference voltage pin
Expansion
Connector
Remarks
-
for video signal input
C14
REXT
A/D converter reference voltage pin for video
-
22k Ω±1%
signal input
C15
C16
Vss
P1_5 / SDA2 / DV1_CLK / CRx4 /
SDA2
IRQ5 / VIO_CLK /
Connected to DAC (AK4353) 1 and 2
P1_1 / SDA0 / DV0_DATA17 /
DV1_CLK
Connected to DV1 input connector
SDA0
Connected to HCI connectoro
TCLKC / IRQ1 / VIO_HD /
CN8-13
Connected to LCD0 output connector
DV0_HSYNC
C18
CN8-17
Connected to MOST I/F connector
LCD1_EXTCLK
C17
Connected to EEPROM
Connected to CMOS camera input connector
P2_14 / D30 / MOSI0 /
SPBIO21_0
Connected to serial flash memory 2
DV0_DATA14 / SPBIO21_0 /
LCD1_DATA14
Connected to LCD1 output connector
ET_RXD1
Connected to Ethernet PHY
CN8-10
CRx4 / TxD0 / LCD1_DATA14 /
IRQ0
C19
PVcc
C20
Vss
C21
P2_9 / D25 / ET_RXD1 /
-
DV0_DATA9 / SSIWS0 / LRXD0 /
SW2-1:ON
JP3:Open
LCD1_DATA9 / VIO_D9 / SSL40
LRXD0
Connected to LIN connector
LCD1_DATA9
Connected to LCD1 output connector
P2_7 / D23 / ET_TXD3 /
ET_TXD3
Connected to Ethernet PHY
-
SW2-1:ON
DV0_DATA7 / SSITxD5 /
SSITxD5
Connected to HCI connector
CN7-29
SW2-1:OFF
D7
Data bus
CN1-12
D6
Data bus
CN1-13
D3
Data bus
CN1-17
D1
Data bus
CN1-19
CN7-31
SW2-1:OFF
JP3:Short
SW2-1:OFF
JP3:Open
C22
IETxD/RTS1 / VIO_D7 /
LCD0_DATA23
D1
P6_7 / D7 / LCD1_DATA15 /
LCD0_TCON6 / RxD5 / MISO1 /
DV0_DATA23
D2
P6_6 / D6 / LCD1_DATA14 /
LCD0_TCON5 / TxD5 / MOSI1 /
DV0_DATA22
D3
Vcc
D4
Vss
D5
P6_3 / D3 / LCD1_DATA11 /
LTXD1 / IRQ2 / CTS5 / TIOC2B /
TxD2 / DV0_DATA19
D6
P6_1 / D1 / LCD1_DATA9 /
LTXD0 / IRQ4 / TIOC1B /
SSIDATA4 / TxD3 / DV0_DATA17
D7
PVcc
D8
PVcc
D9
LVDSPLLVcc
D10
Vss
D11
LVDSREFRIN
D12
LVDSAPVcc
D13
Vcc
D14
VRP
-
A/D converter TOP reference voltage pin for
5.6k Ω±1%
-
video signal input
D15
Vss
D16
PVcc
: 3.3V system power supply,
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
: 1.18V system power supply,
: GND, Letters in Red indicate CPU board setting.
2-5
R7S72100 CPU (GENMAI) Optional Board
Table 2.2.5
Pin
No.
PVcc
D18
PVcc
D19
Vss
D20
2.
Functional Specification
RTK7721000B00000BR Pin Functions (5)
Pin Name
D17
RTK7721000B00000BR
Function
Description
Expansion
Connector
Remarks
P2_8 / D24 / ET_RXD0 /
ET_RXD0
Connected to Ethernet PHY
-
SW2-1:ON
DV0_DATA8 /SSISCK0 /
LCD1_DATA8
Connected to LCD1 output connector
CN7-32
SW2-1:OFF
CN7-11
LCD0_TCON6 / LCD1_DATA8 /
VIO_D8 / RSPCK4
D21
D22
E1
P10_15 / DV0_DATA11 /
DV0_DATA11
Connected to DV0 input connector
SSITxD1 / MISO0 /
LCD0_DATA8
Connected to LCD0 output connector
LCD0_DATA8 / VIO_D11
VIO_D11
Connected to CMOS camera input connector
P10_14 / DV0_DATA10 /
DV0_DATA10
Connected to DV0 input connector
SSIRxD1 / MOSI0 /
LCD0_DATA9
Connected to LCD0 output connector
CN7-12
LCD0_DATA9 / VIO_D10
VIO_D10
Connected to CMOS camera input connector
P6_10 / D10 / DV0_DATA14 /
D10
Data bus
CN1-8
D9
Data bus
CN1-9
D8
Data bus
CN1-10
LCD0_TCON5 / RxD0 /
LCD0_DATA2 / IRQ2
E2
P6_9 / D9 / DV0_DATA13 /
TxD0 / LCD0_DATA1 / IRQ1
E3
P6_8 / D8 / DV0_DATA12 /
CAN_CLK / SCK0 /
LCD0_DATA0 / IRQ0
E4
Vcc
E19
P2_11 / D27 / ET_RXD3 /
ET_RXD3
Connected to Ethernet PHY
-
SW2-1:ON
DV0_DATA11 /SSITxD0 /
P2_11
Connected to LIN connector (sleep control)
CN7-33
SW2-1:OFF
TIOC1A / LCD1_DATA11 /
LCD1_DATA11
Connected to LCD1 output connector
P2_6 / D22 / ET_TXD2 /
ET_TXD2
Connected to Ethernet PHY
-
SW2-1:ON
DV0_DATA6 / SSIRxD5 / RxD1 /
SSIRxD5
Connected to HCI connector
CN7-30
SW2-1:OFF
P10_12 / DV0_DATA8 /
DV0_DATA8
Connected to DV0 input connector
CN7-10
SSISCK1 / RSPCK0 /
LCD0_DATA11
Connected to LCD0 output connector
VIO_D11 / MISO4
E20
VIO_D6 / LCD0_DATA22
E21
E22
LCD0_DATA11 / VIO_D8
VIO_D8
Connected to CMOS camera input connector
P2_5 / D21 / ET_TXD1 /
ET_TXD1
Connected to Ethernet PHY
-
SW2-1:ON
DV0_DATA5 / SSIWS5 /
SSIWS5
Connected to HCI connector
CN7-27
SW2-1:OFF
D14
Data bus
CN1-3
D13
Data bus
CN1-4
D11
Data bus
CN1-7
SPBSSL_1 / TxD1 / VIO_D5 /
LCD0_DATA21
F1
P6_14 / D14 / DV0_DATA22 /
TxD6 / LCD0_DATA6 / IRQ6
F2
P6_13 / D13 / DV0_DATA21 /
SCK6 / RXD1 / LCD0_DATA5 /
IRQ5
F3
P6_11 / D11 / DV0_DATA15 /
LCD0_TCON6 / SCK1 /
LCD0_DATA3 / IRQ3
F4
Vcc
F19
P2_4 / D20 / ET_TXD0 /
ET_TXD0
Connected to Ethernet PHY
-
SW2-1:ON
DV0_DATA4 / SSISCK5 /
SSISCK5
Connected to HCI connector
CN7-28
SW2-1:OFF
CN7-9
SPBCLK_1 / SCK1 / VIO_D4 /
LCD0_DATA20
F20
P10_13 / DV0_DATA9 /
DV0_DATA9
Connected to DV0 input connector
SSIWS1 / SSL00 /
LCD0_DATA10
Connected to LCD0 output connector
LCD0_DATA10 / VIO_D9
VIO_D9
Connected to CMOS camera input connector
: 3.3V system power supply,
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
: 1.18V system power supply,
: GND, Letters in Red indicate CPU board setting.
2-6
R7S72100 CPU (GENMAI) Optional Board
Table 2.2.6
Pin
No.
F21
RTK7721000B00000BR
2.
Functional Specification
RTK7721000B00000BR Pin Functions (6)
Pin Name
Function
Description
Expansion
Connector
Remarks
P2_2 / D18 / ET_TXEN /
ET_TXEN
Connected to Ethernet PHY
-
SW2-1:ON
DV0_DATA2 / SPBIO20_1 /
MLB_SIG
Connected to MOST I/F connector
CN7-26
SW2-1:OFF
CN7-19
MLB_SIG / TIOC2B / VIO_D2 /
LCD0_DATA18
F22
P4_15 / LCD0_DATA23 /
SD_D2_0
Connected to SD card slot
LCD1_TCON2 / SD_D2_0 /
LCD1_TCON2
Connected to LCD1 output connector
MMC_D2 / SPBIO31_1 /
SSITxD3
Connected to DAC (AK4353) 1
LCD0_TCON1
Connected to LCD0 output connector
CN2-19
LCD0_TCON2
Connected to LCD0 output connector
CN2-20
D15
Data bus
CN1-2
D12
Data bus
CN1-5
CN7-20
SSITxD3 / RxD2 / IRQ7
G1
P11_13 / CTx1 / SSL10 /
LCD0_TCON4 / MMC_D5 /
LCD0_TCON1
G2
P11_12 / CRx1 / RSPCK1 /
IRQ3 / MMC_D4 / LCD0_TCON2
G3
P6_15 / D15 / DV0_DATA23 /
RxD6 / LCD0_DATA7 / IRQ7
G4
P6_12 / D12 / DV0_DATA20 /
TXD1 / LCD0_DATA4 / IRQ4
G19
P4_14 / LCD0_DATA22 /
SD_D3_0
Connected to SD card slot
LCD1_TCON1 / SD_D3_0 /
LCD1_TCON1
Connected to LCD1 output connector
MMC_D3 / SPBIO21_1 /
P4_14
Connected to DAC (AK4353) 1 and 2
SSIRxD3 / TxD2 / IRQ6
G20
P2_3 / D19 / ET_CRS /
ET_CRS
Connected to Ethernet PHY
-
SW2-1:ON
DV0_DATA3 / SPBIO30_1 /
P2_3
Connected to MOST I/F connector (reset
CN7-25
SW2-1:OFF
IERxD / CTS1 / VIO_D3 /
control)
LCD0_DATA19
G21
P4_13 / LCD0_DATA21 /
SD_CMD_0
Connected to SD card slot
LCD1_TCON0 / SD_CMD_0 /
LCD1_TCON0
Connected to LCD1 output connector
MMC_CMD / SPBIO11_1 /
SSIWS3
Connected to DAC (AK4353) 1
P7_2 / RAS / DV0_DATA18 /
RAS
Connected to SDRAM 1 and 2
ET_TXER / RXD4 / CRx2 /
CRx2
Connected to CAN transceiver
CS3
Connected to SDRAM 2
CN2-29
LCD0_TCON0
Connected to LCD0 output connector
CN2-18
MD_BOOT2
Connected to DIPSW as a boot mode input
CN2-30
CS0
Connected to NOR flash memory 1
P4_11 / LCD0_DATA19 /
SD_D0_0
Connected to SD card slot
LCD1_TCON6 / SD_D0_0 /
LCD1_TCON6
Connected to LCD1 output connector
CN7-17
SSIWS3 / RxD1 / IRQ5
G22
H1
Vss
CN2-28
JP1:Open
JP1:Short
SSIWS1 / TIOC0C
H2
P7_1 / CS3 / DV0_DATA17 /
ET_TXCLK / TXD4 / DV0_CLK /
SSISCK1 / TIOC0B
H3
P11_14 / SPDIF_IN / MOSI1 /
LCD0_TCON5 / MMC_D6 /
LCD0_TCON0
H4
P7_0 / MD_BOOT2 / CS0 /
DV0_DATA16 / ET_MDC /
SCK4 / LTXD0 / TIOC0A
H19
SW1-3
JP5:1-2
JP5:2-3
CN7-15
MMC_D0 / SSITxD5 / CTx4 /
SCK1 / IRQ3
H20
H21
P10_11 / DV0_DATA7 / TIOC2B /
DV0_DATA7
Connected to DV0 input connector
ET_RXD3 / LCD0_DATA12 /
LCD0_DATA12
Connected to LCD0 output connector
VIO_D7
VIO_D7
Connected to CMOS camera input connector
P10_10 / DV0_DATA6 / TIOC2A /
DV0_DATA6
Connected to DV0 input connector
ET_RXD2 / LCD0_DATA13 /
LCD0_DATA13
Connected to LCD0 output connector
VIO_D6
VIO_D6
Connected to CMOS camera input connector
: 3.3V system power supply,
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
: 1.18V system power supply,
CN7-7
CN7-8
: GND, Letters in Red indicate CPU board setting.
2-7
R7S72100 CPU (GENMAI) Optional Board
Table 2.2.7
Pin
No.
H22
RTK7721000B00000BR
2.
Functional Specification
RTK7721000B00000BR Pin Functions (7)
Pin Name
Function
Description
Expansion
Connector
P4_12 / LCD0_DATA20 /
SD_CLK_0
Connected to SD card slot
LCD1_CLK / SD_CLK_0 /
LCD1_CLK
Connected to LCD1 output connector
MMC_CLK / SPBIO10_1 /
SSISCK3
Connected to DAC (AK4353) 1
P7_5 / RD/WR / DV0_DATA21 /
RD/WR
Connected to SDRAM 1 and 2
ET_TXD1 / RXD7 / SSISCK2 /
RxD7
Connected to HCI connector
P7_4 / CKE / DV0_DATA20 /
CKE
Connected to SDRAM 1 and 2
ET_TXD0 / TXD7 / SSITxD1 /
TxD7
Connected to HCI connector
P7_3 / CAS / DV0_DATA19 /
CAS
Connected to SDRAM 1 and 2
ET_TXEN / SCK7 / CTx2 /
CTx2
Connected to CAN transceiver
LCD0_CLK
Connected to LCD0 output connector
CN2-17
CN7-5
Remarks
CN7-18
SSISCK3 / TxD1 / IRQ4
J1
CN2-25
TIOC1B
J2
CN2-26
TIOC1A
J3
CN2-27
SSIRxD1 / TIOC0D
J4
P11_15 / SPDIF_OUT / MISO1 /
IRQ1 / MMC_D7 / LCD0_CLK
J9
Vss
J10
Vss
J11
Vss
J12
Vss
J13
Vss
J14
Vss
J19
Vcc
J20
P10_9 / DV0_DATA5 / TIOC1B /
DV0_DATA5
Connected to DV0 input connector
ET_RXD1 / LCD0_DATA14 /
LCD0_DATA14
Connected to LCD0 output connector
J21
J22
VIO_D5
VIO_D5
Connected to CMOS camera input connector
P10_8 / DV0_DATA4 / TIOC1A /
DV0_DATA4
Connected to DV0 input connector
ET_RXD0 / LCD0_DATA15 /
LCD0_DATA15
Connected to LCD0 output connector
CN7-6
VIO_D4
VIO_D4
Connected to CMOS camera input connector
P4_10 / LCD0_DATA18 /
SD_D1_0
Connected to SD card slot
LCD1_TCON5 / SD_D1_0 /
LCD1_TCON5
Connected to LCD1 output connector
A1
Address bus
CN3-30
WE1/DQMLU
Connected to SDRAM 1 and 2
CN2-23
CN7-16
MMC_D1 / SSIRxD5 / RxD0 /
IRQ2
K1
P7_9 / A1 / SSIWS3 / ET_RXD0 /
CTx0 / TIOC3B / IRQ0
K2
P7_7 / WE1/DQMLU /
DV0_DATA23 / ET_TXD3 /
K3
Connected to NOR flash memory 1 and 2
RTS7 / SSIDATA2 / TIOC2B
RTS7
Connected to HCI connector
P7_6 / WE0/DQMLL /
WE0/DQMLL
Connected to SDRAM 1 and 2
DV0_DATA22 / ET_TXD2 /
CTS7
Connected to HCI connector
CN2-24
CTS7 / SSIWS2 / TIOC2A
K4
P7_8 / RD / SSISCK3 / CRx0 /
RD
Connected to NOR flash memory 1 and 2
TIOC3A / IRQ1
P7_8
Connected to HCI connector
K9
Vss
K10
Vss
K11
Vss
K12
Vss
K13
Vss
K14
Vss
K19
Vcc
: 3.3V system power supply,
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
: 1.18V system power supply,
CN2-22
: GND, Letters in Red indicate CPU board setting.
2-8
R7S72100 CPU (GENMAI) Optional Board
Table 2.2.8
Pin
No.
K20
RTK7721000B00000BR
2.
Functional Specification
RTK7721000B00000BR Pin Functions (8)
Pin Name
Function
Description
P4_8 / LCD0_DATA16 /
SD_CD_0
Connected to SD card slot
LCD1_TCON3 / SD_CD_0 /
LCD1_TCON3
Connected to LCD1 output connector
P4_9 / LCD0_DATA17 /
SD_WP_0
Connected to SD card slot
LCD1_TCON4 / SD_WP_0 /
LCD1_TCON4
Connected to LCD1 output connector
Expansion
Connector
Remarks
CN7-14
MMC_CD / SSISCK5 / CTx2 /
SCK0 / IRQ0
K21
CN7-13
SSIWS5 / CRx2 / TxD0 / IRQ1
K22
P2_1 / D17 / ET_TXER /
ET_TXER
Connected to Ethernet PHY
-
SW2-1:ON
DV0_DATA1 / SPBIO10_1 /
MLB_DAT
Connected to MOST I/F connector
CN7-23
SW2-1:OFF
CN2-13
MLB_DAT / TIOC2A / VIO_D1 /
LCD0_DATA17
L1
L2
P11_5 / DV0_DATA17 /
DV0_DATA17
Connected to DV0 input connector
SD_WP_0 / SSIWS4 /
SSIWS4
Connected to DAC (AK4353) 2
LCD0_DATA2
LCD0_DATA2
Connected to LCD0 output connector
P7_11 / A3 / SSITxD3 /
A3
Address bus
CN3-28
A2
Address bus
CN3-29
CN2-14
ET_RXD2 / CRx1 / TIOC3D /
IRQ3
L3
P7_10 / A2 / SSIRxD3 /
ET_RXD1 / CTx1 / TIOC3C /
IRQ2
L4
P11_4 / DV0_DATA16 /
DV0_DATA16
Connected to DV0 input connector
SD_CD_0 / SSISCK4 /
SSISCK4
Connected to DAC (AK4353) 2
MMC_CD / LCD0_DATA3
LCD0_DATA3
Connected to LCD0 output connector
P4_7 / LCD0_DATA15 / MISO1 /
SSITxD0
Connected to audio CODEC (WM8978)
TIOC4D / PWM2H / SSITxD0 /
P4_7
L9
Vss
L10
Vss
L11
Vss
L12
Vss
L13
Vss
L14
Vss
L19
PVcc
L20
-
SW2-2:ON
CN6-29
SW2-2:OFF
DV0_DATA15
L21
P2_0 / D16 / ET_TXCLK /
ET_TXCLK
Connected to Ethernet PHY
-
SW2-1:ON
DV0_DATA0 / SPBIO00_1 /
MLB_CLK
Connected to MOST I/F connector
CN7-24
SW2-1:OFF
MLB_CLK / IRQ5 / VIO_D0 /
LCD0_DATA16
L22
P4_6 / LCD0_DATA14 / MOSI1 /
SSIRxD0
Connected to audio CODEC (WM8978)
-
SW2-2:ON
TIOC4C / PWM2G / SSIRxD0 /
P4_6
NC
CN6-30
SW2-2:OFF
A4
Address bus
CN3-27
CN2-12
DV0_DATA14
M1
P7_12 / A4 / SSISCK4 /
ET_RXD3 / TIOC4A / IRQ4
M2
M3
P11_6 / DV0_DATA18 /
DV0_DATA18
Connected to DV0 input connector
SD_D1_0 / SSIDATA4 /
SSIDATA4
Connected to DAC (AK4353) 2
MMC_D1 / LCD0_DATA1
LCD0_DATA1
Connected to LCD0 output connector
P11_7 / DV0_DATA19 /
DV0_DATA19
Connected to DV0 input connector
SD_D0_0 / CTS5 / MMC_D0 /
LCD0_DATA0
Connected to LCD0 output connector
CN2-11
LCD0_DATA0
M4
Vcc
M9
Vss
M10
Vss
M11
Vss
: 3.3V system power supply,
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
: 1.18V system power supply,
: GND, Letters in Red indicate CPU board setting.
2-9
R7S72100 CPU (GENMAI) Optional Board
Table 2.2.9
Pin
No.
RTK7721000B00000BR
2.
Functional Specification
RTK7721000B00000BR Pin Functions (9)
Pin Name
Function
Description
Expansion
Connector
Remarks
M12
Vss
M13
Vss
M14
Vss
M19
PVcc
M20
P4_5 / LCD0_DATA13 / SSL10 /
SSIWS0
Connected to audio CODEC (WM8978)
-
SW2-2:ON
TIOC4B / PWM2F / SSIWS0 /
P4_5
NC
CN6-27
SW2-2:OFF
P4_4 / LCD0_DATA12 /
SSISCK0
Connected to audio CODEC (WM8978)
-
SW2-2:ON
RSPCK1 / TIOC4A / PWM2E /
P4_4
NC
CN6-28
SW2-2:OFF
P10_7 / DV0_DATA3 / TIOC0D /
DV0_DATA3
Connected to DV0 input connector
CN6-23
PWM2H / ET_TXD3 /
LCD0_DATA16
Connected to LCD0 output connector
LCD0_DATA16 / VIO_D3
VIO_D3
Connected to CMOS camera input connector
P7_13 / A5 / SSIWS4 /
A5
Address bus
CN3-26
A6
Address bus
CN3-25
A7
Address bus
CN3-24
CN6-22
DV0_DATA13
M21
SSISCK0 / DV0_DATA12
M22
N1
ET_MDIO / TIOC4B / IRQ5
N2
P7_14 / A6 / SSIDATA4 /
ET_CRS / TIOC4C / IRQ6
N3
P7_15 / A7 / RSPCK0 /
ET_RXCLK / CTS5 / SCI_TXD0 /
TIOC4D
N4
PVcc
N9
Vss
N10
Vss
N11
Vss
N12
Vss
N13
Vss
N14
Vss
N19
N20
N21
N22
P10_4 / DV0_DATA0 / TIOC0A /
DV0_DATA0
Connected to DV0 input connector
PWM2E / ET_TXD0 /
LCD0_DATA19
Connected to LCD0 output connector
LCD0_DATA19 / VIO_D0
VIO_D0
Connected to CMOS camera input connector
P10_5 / DV0_DATA1 / TIOC0B /
DV0_DATA1
Connected to DV0 input connector
PWM2F / ET_TXD1 /
LCD0_DATA18
Connected to LCD0 output connector
LCD0_DATA18 / VIO_D1
VIO_D1
Connected to CMOS camera input connector
P10_6 / DV0_DATA2 / TIOC0C /
DV0_DATA2
Connected to DV0 input connector
PWM2G / ET_TXD2 /
LCD0_DATA17
Connected to LCD0 output connector
LCD0_DATA17 / VIO_D2
VIO_D2
Connected to CMOS camera input connector
P4_3 / LCD0_DATA11 / TIOC0D /
FWE
Connected to NAND flash memory
FWE / CTx3 / RxD2 / MISO4 /
MMC_D7
Connected to MMC card slot
MMC_D7
MISO4
CN6-21
CN6-24
CN6-17
Connected to audio CODEC (WM8978)
Connected to CD deck connector
P1
P8_0 / A8 / SSL00 / ET_RXER /
A8
Address bus
CN3-23
A9
Address bus
CN3-21
A10
Address bus
CN3-20
SCK5 / SCI_SCK0
P2
P8_1 / A9 / MOSI0 / ET_RXDV /
TXD5 / SCI_RXD0
P3
P8_2 / A10 / MISO0 / RXD5 /
IRQ0
P4
PVcc
P9
Vss
P10
Vss
P11
Vss
P12
Vss
P13
Vss
: 3.3V system power supply,
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
: 1.18V system power supply,
: GND, Letters in Red indicate CPU board setting.
2-10
R7S72100 CPU (GENMAI) Optional Board
Table 2.2.10
2.
Functional Specification
RTK7721000B00000BR Pin Functions (10)
Pin
No.
P14
RTK7721000B00000BR
Pin Name
Function
Description
Expansion
Connector
Remarks
Vss
P19
Vss
P20
P4_0 / LCD0_DATA8 / TIOC0A /
FRE
Connected to NAND flash memory
FRE / RSPCK4 / MMC_D4
MMC_D4
Connected to MMC card slot
RSPCK4
Connected to audio CODEC (WM8978)
P4_2 / LCD0_DATA10 / TIOC0C /
FALE
Connected to NAND flash memory
FALE / CRx3 / TxD2 / MOSI4 /
MMC_D6
Connected to MMC card slot
MMC_D6
MOSI4
Connected to audio CODEC (WM8978)
P4_1 / LCD0_DATA9 / TIOC0B /
FCLE
Connected to NAND flash memory
FCLE / SCK2 / SSL40 / MMC_D5
MMC_D5
Connected to MMC card slot
SSL40
Connected to audio CODEC (WM8978)
P8_3 / A11 / DV1_DATA0 /
A11
Address bus
CN3-19
A12
Address bus
CN3-18
A13
Address bus
CN3-17
CN6-11
CN6-16
Connected to CD deck connector
P21
CN6-18
Connected to CD deck connector
P22
R1
CN6-15
JP10:Open
JP10:Short
RSPCK2 / RTS5 / IRQ1 / SCK2
R2
P8_4 / A12 / DV1_DATA1 /
SSL20 / IERxD / RxD2
R3
P8_5 / A13 / DV1_DATA2 /
MOSI2
R4
Vcc
R19
Vcc
R20
R21
P3_15 / LCD0_DATA7 / NAF7 /
NAF7
Connected to NAND flash memory
TRACECTL / SD_D2_1 /
SD_D2_1
Connected to MMC card slot
MMC_D2
MMC_D2
P3_14 / LCD0_DATA6 / NAF6 /
NAF6
Connected to NAND flash memory
TRACECLK / SD_D3_1 /
SD_D3_1
Connected to MMC card slot
MMC_D3
MMC_D3
TRACECLK
R22
T1
CN6-12
Connected to UDI connector
P3_13 / LCD0_DATA5 / NAF5 /
NAF5
Connected to NAND flash memory
AUDIO_XOUT / SD_CMD_1 /
SD_CMD_1
Connected to MMC card slot
MMC_CMD
MMC_CMD
P11_8 / DV0_DATA20 /
DV0_DATA20
Connected to DV0 input connector
SD_CLK_0 / RTS5 / MMC_CLK /
LCD0_TCON6
Connected to LCD0 output connector
P11_9 / DV0_DATA21 /
DV0_DATA21
Connected to DV0 input connector
SD_CMD_0 / SCK5 /
LCD0_TCON5
Connected to LCD0 output connector
P11_10 / DV0_DATA22 /
DV0_DATA22
Connected to DV0 input connector
SD_D3_0 / TxD5 / MMC_D3 /
LCD0_TCON4
Connected to LCD0 output connector
CN6-9
CN2-8
LCD0_TCON6
T2
CN2-7
MMC_CMD / LCD0_TCON5
T3
CN2-6
LCD0_TCON4
T4
Vcc
T19
Vcc
T20
P3_10 / LCD0_DATA2 / NAF2 /
NAF2
Connected to NAND flash memory
TRACEDATA2 / TIOC4C /
SD_D1_1
Connected to MMC card slot
SD_D1_1 / MMC_D1
MMC_D1
TRACEDATA2
T21
Connected to UDI connector
P3_11 / LCD0_DATA3 / NAF3 /
NAF3
Connected to NAND flash memory
TRACEDATA3 / TIOC4D /
SD_D0_1
Connected to MMC card slot
SD_D0_1 / MMC_D
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
CN6-3
MMC_D0
TRACEDATA3
: 3.3V system power supply,
CN6-4
Connected to UDI connector
: 1.18V system power supply,
: GND, Letters in Red indicate CPU board setting.
2-11
R7S72100 CPU (GENMAI) Optional Board
Table 2.2.11
2.
Functional Specification
RTK7721000B00000BR Pin Functions (11)
Pin
No.
T22
RTK7721000B00000BR
Pin Name
Function
Description
P3_12 / LCD0_DATA4 / NAF4 /
NAF4
Connected to NAND flash memory
SD_CLK_1 / MMC_CLK
SD_CLK_1
Connected to MMC card slot
Expansion
Connector
Remarks
CN6-10
MMC_CLK
U1
U2
Vss
P8_6 / A14 / DV1_DATA3 /
A14
Address bus
CN3-16
P11_11 / DV0_DATA23 /
DV0_DATA23
Connected to DV0 input connector
CN2-5
SD_D2_0 / RxD5 / MMC_D2 /
LCD0_TCON3
Connected to LCD0 output connector
A15
Address bus
CN3-15
TD0
Test data output
-
Test clock
-
Connected to SDRAM 1 and 2
CN2-2
CN3-14
MISO2 / IETxD / TxD2
U3
LCD0_TCON3
U4
P8_7 / A15 / DV1_DATA4 /
AUDIO_XOUT / IRQ5 / ET_COL
U19
Vcc
U20
JP0_1 / TDO
U21
TCK
U22
Vss
V1
CKIO
V2
P8_8 / A16 / DV1_DATA5 /
A16
Address bus
SPBIO00_1 / SPDIF_IN /
SPDIF_IN
Connected to TOSLINK connector
P8_9 / A17 / DV1_DATA6 /
A17
Address bus
SPBIO10_1 / SPDIF_OUT /
SPDIF_OUT
Connected to TOSLINK connector
JP2:1-2
JP2:2-3
TIOC1A / PWM1A / TxD3 /
SSISCK5
V3
CN3-12
TIOC1B / PWM1B / RxD3 /
SSIWS5
V4
P8_13 / A21 / SPBSSL_1 /
A21
Address bus
TIOC3D / TXD5 / PWM1F /
SPBSSL_1
Connected to serial flash memory 3
CN3-8
JP8:Open
JP8:Short
SGOUT_3 / SSIWS4
V19
P3_8 / LCD0_DATA0 / NAF0 /
NAF0
Connected to NAND flash memory
TRACEDATA0 / TIOC4A /
SD_CD_1
Connected to MMC card slot
SD_CD_1 / MMC_CD
MMC_CD
TRACEDATA0
V20
TRST#
V21
JP0_0 / TDI
V22
TMS
TDI
CN6-2
Connected to UDI connector
Initialization signal input pin
-
Test data input
-
Test mode select
CN3-11
W1
Vss
W2
P8_10 / A18 / DV1_DATA7 /
A18
Address bus
SPBIO20_1 / TIOC3A / CTx4 /
SPBIO20_1
Connected to serial flash memory 3
P8_11 / A19 / SPBIO30_1 /
A19
Address bus
TIOC3B / RxD5 / PWM1D /
SPBIO30_1
Connected to serial flash memory 3
PWM1C / SGOUT_0 / SSITxD5
W3
CN3-10
SGOUT_1 / DV0_CLK
W4
PVcc
W5
PVcc
W6
PVcc
W7
Vss
W8
Vss
W9
Vcc
W10
Vcc
W11
Vss
W12
PVcc
W13
PVcc
W14
PLLVcc
: 3.3V system power supply,
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
: 1.18V system power supply,
: GND, Letters in Red indicate CPU board setting.
2-12
R7S72100 CPU (GENMAI) Optional Board
Table 2.2.12
Pin
No.
RTK7721000B00000BR
2.
Functional Specification
RTK7721000B00000BR Pin Functions (12)
Pin Name
Function
Description
Expansion
Connector
W15
Vss
W16
Vss
W17
AVss
CN5-13, 14
W18
AVcc
CN5-9, 10
W19
PVcc
W20
P3_9 / LCD0_DATA1 / NAF1 /
NAF1
Connected to NAND flash memory
TRACEDATA1 / TIOC4B /
SD_WP_1
Connected to MMC card slot
SD_WP_1 / IRQ6
TRACEDATA1
CN6-1
Connected to UDI connector
W21
AUDIO_X2
Open
-
W22
AUDIO_X1
Connects audio external clock
CN3-9
Y1
Remarks
P8_12 / A20 / SPBCLK_1 /
A20
Address bus
TIOC3C / SCK5 / PWM1E /
SPBCLK_1
Connected to serial flash memory 3
22.5792MHz
SGOUT_2 / SSISCK4
Y2
P8_14 / A22 / SPBIO01_0 /
A22
Address bus
SPBIO00_1 / TIOC2A / RSPCK2 /
SPBIO01_0
Connected to serial flash memory 3
CN3-7
LCD1_EXTCLK
Connects external clock for LCD panel
CS1
Connected to NOR flash memory 2
P3_4 / LCD0_TCON3 /
ET_RXCLK
Connected to Ethernet PHY
-
SW2-1:ON
ET_RXCLK / SSISCK1 /
SSISCK1
Connected to CD deck connector
CN4-12
SW2-1:OFF
SCI_SCK0
Connected to SIM card slot
SCK3
Connected to UART connector
DV0_HSYNC
Connected to DV0 input connector
PWM2C / ET_TXEN /
LCD0_DATA21
Connected to LCD0 output connector
LCD0_DATA21 / VIO_HD
VIO_HD
Connected to CMOS camera input connector
P3_2 / LCD0_TCON1 /
RxD2
Connected to D-sub 9-pin connector via
PWM1G / TxD4 / SSIDATA4
Y3
PVcc
Y4
P3_7 / LCD0_TCON6 / SSITxD1 /
CN4-13
LCD1_EXTCLK /
SCI_CTS0/RTS0 / TIOC3D /
X9 (optional)
JP6:1-2
JP6:2-3
CS1 / WDTOVF
Y5
AUDIO_XOUT2 / SCI_SCK0 /
TIOC3A / SCK3
Y6
Y7
P10_2 / DV0_HSYNC / TCLKC /
SW14-7:OFF
ET_TXEN / RxD2 / SCI_RXD1 /
RS-232C transceiver
TEND0 / PWM2C / MOSI3
Connected to USB-miniB connector via USB
SW2-1:OFF
SW14-7:ON
CN4-18
CN4-8
JP12:1-2
JP12:2-3
serial conversion IC
Y8
RES#
Connected to reset input switch
CN4-2
Y9
NMI
Connected to non-maskable interrupt switch
CN4-1
Y10
Vss
Y11
VBUSIN1
USB channel 1 VBUS input
-
JP11
CN5-17, 18
JP9
Y12
VBUSIN0
USB channel 0 VBUS input
Y13
USBAVcc
Transceiver unit analog core power supply
Y14
Vss
Y15
P0_0 / MD_BOOT0
MD_BOOT0
Connected to DIPSW as a boot mode input
-
SW1-1
Y16
P0_1 / MD_BOOT1
MD_BOOT1
Connected to DIPSW as a boot mode input
-
SW1-2
Y17
P1_10 / AN2 / IRQ4 / TCLKB
AN2
Connected to key input switch
CN5-16
P1_13 / AN5 / DV0_HSYNC /
P1_13
Connected to CD deck connector (FLAG6)
CN5-11
P1_15
Connected to Ethernet PHY (INT / GPIO4)
CN5-7
Y18
WAIT
Y19
P1_15 / AN7
Y20
PVcc
Y21
VIDEO_X2
Open
-
Y22
VIDEO_X1
Connects external clock for video decoder
-
AA1
P8_15 / A23 / SPBIO11_0 /
A23
Address bus
CN3-6
SPBIO10_1 / TIOC2B / SSL20 /
SPBIO11_0
Connected to serial flash memory 3
27MHz
PWM1H / RxD4
: 3.3V system power supply,
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
: 1.18V system power supply,
: GND, Letters in Red indicate CPU board setting.
2-13
R7S72100 CPU (GENMAI) Optional Board
Table 2.2.13
Pin
No.
RTK7721000B00000BR
2.
Functional Specification
RTK7721000B00000BR Pin Functions (13)
Pin Name
AA2
PVcc
AA3
P9_1 / A25 / SPBIO31_0 / CRx0 /
Function
Description
Expansion
Connector
Remarks
A25
Address bus
CN3-3
P3_5 / LCD0_TCON4 /
ET_RXER
Connected to Ethernet PHY
-
SW2-1:ON
ET_RXER / SSIWS1 /
SSIWS1
Connected to CD deck connector
CN4-11
SW2-1:OFF
IRQ0 / MISO2
AA4
AUDIO_XOUT3 / SCI_TXD0 /
TIOC3B / TxD3
SW14-7:OFF
SCI_TXD0
Connected to SIM card slot
SW2-1:OFF
SW14-7:ON
JP1:Short
Connected to IrDA module
SW2-1:OFF
SW14-7:ON
JP1:Open
TxD3
Connected to UART connector
SW2-1:OFF
SW14-7:ON
JP1:Open
AA5
AA6
P10_1 / DV0_VSYNC / TCLKB /
DV0_VSYNC
Connected to DV0 input connector
CN4-19
PWM2B / ET_TXER /
LCD0_DATA22
Connected to LCD0 output connector
LCD0_DATA22 / VIO_VD
VIO_VD
Connected to CMOS camera input connector
P3_3 / LCD0_TCON2 /
ET_MDIO
Connected to Ethernet PHY
-
SW2-1:ON
ET_MDIO / IRQ4 / BS /
P3_3
Connected to CD deck connector (SSL40)
CN4-7
SW2-1:OFF
SCI_CTS1 / RTS1 / DACK0 /
SW14-7:OFF
PWM2D / MISO3
Connected to SIM card slot (reset)
SW2-1:OFF
SW14-7:ON
AA7
P3_1 / LCD0_TCON0 /
IRQ6
ET_TXER / IRQ6 / TxD2 /
SCI_TXD1 / AUDIO_CLK /
Connected to interrupt switch
-
JP3:1-2
Connected to CD deck connector
CN4-5
JP3:2-3
32.768KHz
AUDIO_CLK
Connected to HCI connector
Connects RTC resonator
-
RTC_X4
Open
-
PWM2B / SSL30
AA8
RTC_X2
AA9
P0_5 / RTC_X4
AA10
Vss
AA11
DM_1
USB channel 1 differential signal D- data
-
AA12
DP_0
USB channel 0 differential signal D+ data
-
AA13
REFRIN
Reference input
-
AA14
Vss
AA15
USB_X2
Open
-
AA16
XTAL
Open
-
AA17
P1_8 / AN0 / IRQ2 / DREQ0 /
Connected to key input switch
CN5-20
AN0
5.6k Ω±1%
VIO_D14 / DV0_DATA14
AA18
P1_11 / AN3 / IRQ5 / TCLKD
AN3
Connected to key input switch
CN5-15
AA19
P1_14 / AN6 / ET_COL
ET_COL
Connected to Ethernet PHY
CN5-8
AA20
AVcc
AA21
PVcc
AA22
BSCANP
CN5-9, 10
Connected to DIPSW as a pin for boundary
-
SW2-3
scan mode setting
AB1
PVcc
AB2
P9_0 / A24 / SPBIO21_0 / CTx0 /
A24
Address bus
CN3-5
TCLKC / MOSI2
: 3.3V system power supply,
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
: 1.18V system power supply,
: GND, Letters in Red indicate CPU board setting.
2-14
R7S72100 CPU (GENMAI) Optional Board
Table 2.2.14
2.
Functional Specification
RTK7721000B00000BR Pin Functions (14)
Pin
No.
AB3
RTK7721000B00000BR
Pin Name
Function
Description
Expansion
Connector
Remarks
P3_6 / LCD0_TCON5 /
ET_RXDV
Connected to Ethernet PHY
-
SW2-1:ON
ET_RXDV / SSIRxD1 /
SSIRxD1
Connected to CD deck connector
CN4-14
SW2-1:OFF
SCI_RXD0
Connected to SIM card slot
SCI_RXD0 / TIOC3C / RxD3
SW14-7:OFF
SW2-1:OFF
SW14-7:ON
JP1:Short
JP5:Open
Connected to IrDA module
SW2-1:OFF
SW14-7:ON
JP1:Open
JP5:Short
RxD3
Connected to UART connector
SW2-1:OFF
SW14-7:ON
JP1:Open
JP5:Open
AB4
AB5
P10_0 / DV0_CLK / TCLKA /
DV0_CLK
Connected to DV0 input connector
PWM2A / ET_TXCLK /
LCD0_DATA23
Connected to LCD0 output connector
LCD0_DATA23 / VIO_CLK
VIO_CLK
Connected to CMOS camera input connector
P10_3 / TCLKD / PWM2D /
LCD0_DATA20
Connected to LCD0 output connector
ET_CRS / LCD0_DATA20 /
P10_3
Connected to CMOS camera input connector
VIO_FLD
AB6
P3_0 / LCD0_CLK /
ET_TXCLK / IRQ2 / SCK2 /
SCI_SCK1 / TxD2 / PWM2A /
RSPCK3
CN4-20
CN4-17
JP4:2-3
(reset control)
TxD2
Connected to D-sub 9-pin connector via
CN4-6
JP13:1-2
RS-232C transceiver
Connected to USB-miniB connector via USB
JP13:2-3
serial conversion IC
AB7
Vss
AB8
RTC_X1
AB9
P0_4 / RTC_X3
AB10
Vss
AB11
AB12
AB13
Vss
AB14
USBAPVcc
Transceiver unit analog pin power supply
AB15
USB_X1
Connects USB external clock
-
48MHz
AB16
EXTAL
Connects crystal resonator as a system clock
-
13.33MHz
Connects RTC resonator
-
32.768KHz
Connects RTC external clock
-
4MHz
DP_1
USB channel 1 differential signal D+ data
-
DM_0
USB channel 0 differential signal D- data
-
RTC_X3
source
AB17
Vss
AB18
P1_9 / AN1 / IRQ3 / VIO_D15 /
AN1
Connected to key input switch
CN5-19
P1_12
Connected to CD deck connector (TRANS)
CN5-12
DV0_DATA15
AB19
P1_12 / AN4 / DV0_VSYNC /
VIO_FLD
AB20
AVss
AB21
AVref
AB22
Vss
: 3.3V system power supply,
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
CN5-13, 14
ADC analog reference voltage
: 1.18V system power supply,
: GND, Letters in Red indicate CPU board setting.
2-15
R7S72100 CPU (GENMAI) Optional Board
2.2.3
RTK7721000B00000BR
2.
Functional Specification
RTK7721000B00000BR Module Applicability
The symbol of "Y" in the table indicates that both modules can be used in combination, and the "N" indicates that
combination use is not applicable.
Table 2.2.15 lists the RTK7721000B00000BR Module Applicability.
RTK7721000B00000BR Module Applicability
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Digital video signal input 1 (ch0)
CMOS camera input
LCD output (LCD0_EXTCLK)
LCD output 2 (ch1)
Y
Y
*2
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
Y
N
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
*3
Y
Y
Y
*3
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
N
N
N
Y
Y
N
N
Y
Y
N
N
Y
Y
Y Y
Y Y N
N Y Y Y
J18
Y
Y
Y
N
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
N
N
N
N
N
N
N
Y
Y
Y
Y
N
Y
Y
Y
Y
J17
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
X1
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
J12~J14, J16
Audio DAC2
LCD output 1 (ch0)
Y
Y
Y
Y
N
Y
N
Y
Y
N
Y
Y
Y
Y
Y
N
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
Y
Y
Y
N
N
Y
J10, J11, J15
Audio DAC1
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
J9
Key input
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
J6
CD deck
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
SW1~SW13
HCI
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
J8
Y
Y
Y
Y
Y
Y
N
Y
Y
N
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
N
Y
N
N
N
Y
Y
N
J7
IEBus
N
N
N
N
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
J5
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
J4
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
J3
UART
IrDA
SIM card slot
Serial port
IRQ6 switch
ARM JTAG 20
CoreSight 20
MOST
TOSLINK
LVDS output
MMC card slot
SD card slot
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
U3
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
J2
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
J17, J19
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
SW6
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
J22
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
J21
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
J3
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
U26
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
J14
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
J15
CAN2
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
N
Y
Y
Y
J11
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
J13
Y
Y
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
J12
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
J4, J6
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
CAN1
Audio CODEC
Video input
Ethernet
USB
EEPROM
LCD output (LCD1_EXTCLK)
Y
*1
Y
Y
Y
Y
Y
Y
Y
Y
Y
X9
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
J1
Y
Y
Y
Y
Y
Y
Y
Y
Y
J10
Y
Y
Y
Y
Y
Y
Y
Y
J5, J8
Y
Y
Y
Y
Y
Y
Y
RTK7721000B00000BR
U10
Serial flash memory 3
NAND flash memory
U9
U4
Part No.
U8
U5
SDRAM2
Y Y N Y
Y Y N Y
Y Y Y Y
Y Y Y
Y
Y Y
Y Y
Y
Y Y Y
Y Y Y Y
Y Y Y Y
Y Y Y Y
Y Y Y Y
Y Y Y Y
Y Y Y N
Y Y Y Y
N Y Y Y
Y Y Y Y
Y Y Y N
Y Y Y N
Y Y Y Y
Y Y Y Y
Y Y Y N
Y Y Y Y
Y Y Y Y
Y Y Y Y
Y Y Y Y
Y Y Y Y
Y Y Y Y
Y Y Y Y
Y Y Y Y
N Y Y Y
Y Y Y N
Y Y Y Y
Y Y Y Y
Y Y Y Y
Y Y Y Y
Y N Y N
Y Y Y Y
Y Y Y Y
Y Y Y Y
Y Y Y N
U6, U7
NOR flash memory 2
Y Y
Y
Y
Y Y
Y Y
N Y
Y Y
Y Y
Y Y
Y Y
Y Y
*1 Y
Y Y
Y Y
Y N
Y Y
Y Y
Y Y
N Y
Y Y
Y Y
Y Y
Y Y
Y Y
Y Y
Y Y
Y Y
Y Y
Y Y
N N
Y Y
Y Y
Y Y
Y Y
Y Y
Y Y
Y *2
Y Y
Y Y
Y Y
SDRAM1
NOR flash memory 1
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
U3
NOR flash memroy 1
NOR flash memory 2
SDRAM1
SDRAM2
Serial flash memory 1 and 2 *4
Serial flash memroy 3
NAND flash memory
EEPROM
USB
Ethernet
Video input
LCD output (LCD1_EXTCLK)
Audio CODEC (WM8978)
CAN1
CAN2
SD card slot (4 bits)
MMC card slot (8 bits)
LVDS output
TOSLINK
MOST
CoreSight 20
ARM JTAG 20
IRQ6 switch
Serial port
SIM card slot
IrDA
UART
IEBus
LIN
HCI
CD deck
Key input
Audio DAC1 (AK4353)
Audio DAC2 (AK4353)
LCD output 1 (ch0)
LCD output 2 (ch1)
LCD output (LCD0_EXTCLK)
CMOS camera input
Digital video signal input 1 (ch0)
Digital video signal input 2 (ch1)
U2
RTK7721000B00000BR
RTK772100BC00000BR
Module Name
Serial flash memory 1 and 2
RTK772100BC00000BR
LIN
Table 2.2.15
*1: P3_7 / CS1 / LCD1_EXTCLK are the common pins. These pins can be used in combination when
LCD1_EXTCLK is not used.
The oscillator should be mounted to X0 on the RTK772100BC00000BR when using LCD1_EXTCLK.
*2: P5_8 / CS2 / LCD0_EXTCLK are the common pins. These pins can be used in combination when
LCD0_EXTCLK is not used.
The oscillator should be mounted to X1 when using LCD0_EXTCLK.
*3: R315 to R318 or R14, R16, R17, R20, R22, R24, R26 and R29 on the RTK772100BC00000BR need to be
removed.
*4: Set SPBCLK_0 less than 33.33MHz or disconnect JP6 when using the serial flash memory 1 and 2 in the
RTK7721000B00000BR connected.
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
2-16
R7S72100 CPU (GENMAI) Optional Board
2.3
RTK7721000B00000BR
2.
Functional Specification
IEBus Interface
The R7S72100 includes a smaller digital data transmission system IEBus controller (EIBB) designed to execute data
transmission between units. The RTK7721000B00000BR connects the R7S72100 IEBB pin to the 4-pin 2.5mm pitch
connector via the IEBus transceiver IC.
Figure 2.3.1 shows the IEBus Interface Block Diagram. Table 2.3.1 lists the RTK772100BC00000BR JP4 Function Setting,
and Table2.3.2 lists the JP7 and JP2 Function Settings.
2
To CAN transceiver
Expansion
connector
2
2
IEBus transceiver
R2A11210SP (U4)
3.3V
R7S72100 (U1)
P5_10 / CTx1 / IETxD /
LCD1_DATA17
P5_9 / ET_MDC / CRx1 / IERxD /
LCD1_DATA16
2
1
3
P5_10
P5_9
P5_9
P5_10
JP7
2
1
3
JP2
IEBus connector
(J4)
5V
To LCD panel I/F2
IERxD
R
BUS+
S1
BUS-
1
2
NC
IETxD
62Ω
3
3.3V
To LAN I/F
S2
JP4
Note: Letters in Red indicate
functions in use.
nSTB
4
5V
Vcc
: Optional
Figure 2.3.1
Table 2.3.1
IEBus Interface Block Diagram
RTK772100BC00000BR JP4 Function Setting
1-2
Jumper
JP4
2-3
Use P5_9 as CRx1 input pin
None
Use P5_9 as ET_MDC output
Use P5_9 as IERxD input pin or
pin (initial setting)
LCD1_DATA16 output pin
indicates setting function.
Table2.3.2
JP7 and JP2 Function Settings
1-2
Jumper
JP7
Use P5_9 as IERxD input pin or
2-3 or Open
Use P5_9 as ET_MDC output pin (initial setting)
LCD1_DATA16 output pin
JP2
Use P5_9 as IERxD input pin
Use P5_9 as LCD1_DATA16 output pin
(initial setting)
indicates setting function.
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
2-17
R7S72100 CPU (GENMAI) Optional Board
2.4
RTK7721000B00000BR
2.
Functional Specification
LIN Interface
The R7S72100 includes a LIN/UART interface (RLIN3). The RTK7721000B00000BR connects the R7S72100 RLIN3 pin
to the 3-pin 2.5mm pitch connector via the LIN transceiver IC.
Figure 2.4.1 shows the LIN Interface Block Diagram. Table2.4.1 lists the SW2-1 (DIP Switch for RTK772100BC00000BR
System Setting) Function Setting, and Table2.4.2 lists the JP3 Function Setting.
4
To LAN I/F
Expansion
connector
3
3
LIN transceiver
MAX13020 (U5)
3.3V
LAN/Option select (U13)
R7S72100 (U1)
P2_8 / ET_RXD0 / LCD1_DATA8
1A
P2_9 / ET_RXD1 / LRXD0 /
LCD1_DATA9
2A
P2_10 / ET_RXD2 / LTXD0 /
LCD1_DATA10
3A
P2_11 / ET_RXD3 /
LCD1_DATA11
1B1
P2_9
1B2
2B1
4A
LIN connector
5V (J5)
To LCD panel I/F2
5V
1
JP3
2
LIN
RXD
3.3V
P2_10
2B2
3B1
P2_9
3B2
4B1
P2_10
4B2
P2_11
3
TXD
5V
P2_11
nSLP
5kΩ
nWAKE
5V
VBAT
MUX
Note: Letters in Red indicate
functions in use.
OE#
: Optional
S
3.3V
DIP
SW2-1
Figure 2.4.1
Table2.4.1
LIN Interface Block Diagram
SW2-1 (DIP Switch for RTK772100BC00000BR System Setting) Function Setting
Function
DIP Switch
ON
SW2-1
OFF
Use P3_[6:3] and P2_[11:0] as Ethernet PHY
Use P3_[6:3] and P2_[11:0] as MOST control pin
control pin (initial setting)
and expansion connector pin
indicates setting function.
Table2.4.2
JP3 Function Setting
Short
Jumper
JP3
Use P2_9 as LRXD0 input pin
Open
Use P2_9 as LCD1_DATA9 output pin
(initial setting)
indicates setting function.
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
2-18
R7S72100 CPU (GENMAI) Optional Board
2.5
RTK7721000B00000BR
2.
Functional Specification
SIM Card Interface
The serial communication interface (SCI) embedded in the R7S72100 responds to the smart card (IC card) interface for the
ISO/IEC7816-3 (Identification Card) as extension with asynchronous communication mode. The RTK7721000B00000BR
connects the R7S72100 SCI pin to the SIM card slot.
Figure 2.5.1 shows the SIM Card Interface Block Diagram. Table2.5.1 lists the SW2-1 (DIP Switch for
RTK772100BC00000BR System Setting) Function Setting, Table2.5.2 lists the SW14-7 (DIP Switch for System Setting)
Function Setting, and Table2.5.3 lists the JP1 and JP5 Function Settings.
4
4
3
To LAN I/F
Expansion
connector
2
4
P3_3 / ET_MDIO
P3_4 / ET_RXCLK / SSISCK1 /
SCI_SCK0 / SCK3
P3_5 / ET_RXER / SSIWS1 /
SCI_TXD0 / TxD3
P3_6 / ET_RXDV / SSIRxD1 /
SCI_RXD0 / RxD3
2A
3A
4A
P3_3
1B2
2B1
P3_3
2B2
3B1
P3_4
3B2
4B1
P3_5
4B2
P3_6
OE#
: Optional
P3_4
1B1
1A
2A
P3_5
3A
P3_6
4A
Table2.5.1
P3_3
1B2
2B1
SCI_SCK0
2B2
3B1
SCI_TXD0
3B2
4B1
SCI_RXD0
C2:Reset
C3:Clock
5V
C1:Vcc
3.3V
3.3V
C6:Vpp
JP1
C7:I/O
C5:GND
4B2
OE#
3.3V
S
3.3V
DIP
SW14-7
SIM Card Interface Block Diagram
SW2-1 (DIP Switch for RTK772100BC00000BR System Setting) Function Setting
Function
DIP Switch
ON
SW2-1
RxD
SIM card slot (J2)
MUX
S
DIP
SW2-1
Figure 2.5.1
SCI_RXD0
JP5
MUX
Note: Letters in Red indicate
functions in use.
To IrDA module
Serial/CD select (U2)
1B1
1A
To UART connector
3.3V
LAN/Option select (U14)
R7S72100 (U1)
To CD deck connector
OFF
Use P3_[6:3] and P2_[11:0] as Ethernet PHY
Use P3_[6:3] and P2_[11:0] as MOST control pin
control pin (initial setting)
and expansion connector pin
indicates setting function.
Table2.5.2
SW14-7 (DIP Switch for System Setting) Function Setting
Function
DIP Switch
ON
SW14-7
Use P3_[6:3] as SCI pin (initial settin)
OFF
Use P3_[6:3] as SSIF pin
indicates setting function.
Table2.5.3
JP1 and JP5 Function Settings
Short
Jumper
JP1
Use SCI in smart card interface mode
Open
Use SCI in serial communication interface mode
(initial setting)
JP5
Connect SCI_RXD0 pin to IrDA module
Do not connect SCI_RXD0 pin to IrDA module
(initial settin)
indicates setting function.
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
2-19
R7S72100 CPU (GENMAI) Optional Board
2.6
RTK7721000B00000BR
2.
Functional Specification
IrDA Module
The R7S72100 includes a serial communication interface (SCI) which transmits/receives the IrDA (infrared Data
Association) communication waveform based on the IrDA standard working with the IrDA module. The
RTK7721000B00000BR connects the R7S72100 SCI pin to the IrDA module.
Figure 2.6.1 shows the IrDA Module Block Diagram. Table2.6.1 lists the SW2-1 (DIP Switch for RTK772100BC00000BR
System Setting) Function Setting, Table2.6.2 lists the SW14-7 (DIP Switch for System Setting) Function Setting, and
Table2.6.3 lists the JP1 and JP5 Function Settings.
4
2
To LAN I/F
Expansion
connector
2
2
2
LAN/Option select (U14)
R7S72100 (U1)
P3_3 / ET_MDIO
1A
P3_4 / ET_RXCLK / SSISCK1 /
SCI_SCK0 / SCK3
2A
P3_5 / ET_RXER / SSIWS1 /
SCI_TXD0 / TxD3
P3_6 / ET_RXDV / SSIRxD1 /
SCI_RXD0 / RxD3
2A
2B2
3B1
P3_5
3B2
4B1
P3_5
4B2
P3_6
P3_6
3A
4A
OE#
: Optional
Table2.6.1
2B2
3B1
SCI_TXD0
3B2
4B1
SCI_RXD0
TxD
JP5
RxD
4B2
OE#
3.3V
S
3.3V
DIP
SW14-7
IrDA Module Block Diagram
SW2-1 (DIP Switch for RTK772100BC00000BR System Setting) Function Setting
Function
DIP Switch
ON
SW2-1
I/O
MUX
S
DIP
SW2-1
Figure 2.6.1
JP1
IrDA module
(U3)
1B2
2B1
MUX
Note: Letters in Red indicate
functions in use.
To SIM card slot
SCI_TXD0
SCI_RXD0
1B1
1A
1B2
2B1
4A
To UART connector
Serial/CD select (U2)
1B1
3A
To CD deck connector
OFF
Use P3_[6:3] and P2_[11:0] as Ethernet PHY
Use P3_[6:3] and P2_[11:0] as MOST control pin
control pin (initial setting)
and expansion connector pin
indicates setting function.
Table2.6.2
SW14-7 (DIP Switch for System Setting) Function Setting
Function
DIP Switch
ON
SW14-7
Use P3_[6:3] as SCI pin (initial setting)
OFF
Use P3_[6:3] as SSIF pin
indicates setting function.
Table2.6.3
JP1 and JP5 Function Settings
Short
Jumper
JP1
Use SCI in smart card interface mode
Open
Use SCI in serial communication interface mode
(initial setting)
JP5
Connect SCI_RXD0 pin to IrDA module
Do not connect SCI_RXD0 pin to IrDA module
(initial setting)
indicates setting function.
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
2-20
R7S72100 CPU (GENMAI) Optional Board
2.7
RTK7721000B00000BR
2.
Functional Specification
UART Interface
The R7S72100 includes a serial communication interface (SCI). The RTK7721000B00000BR connects the R7S72100 SCI
pin to the 5-pin 2.5mm pitch connector.
Figure 2.7.1 shows the UART Interface Block Diagram. Table2.7.1 lists the SW2-1 (DIP Switch for
RTK772100BC00000BR System Setting) Function Setting, and Table2.7.2 lists the SW14-7 (DIP Switch for System
Setting) Function Setting.
3
4
3
To LAN I/F
To CD deck connector
To SIM card slot
TxD3
RxD3
Expansion
connector
3
2
LAN/Option select (U14)
R7S72100 (U1)
P3_3 / ET_MDIO
RxD3
P3_6 / ET_RXDV / SSIRxD1 /
SCI_RXD0 / RxD3
4A
1B1
1A
1B2
2B1
2A
3A
P3_4
2B2
3B1
P3_4
3B2
4B1
P3_5
4B2
P3_6
2A
P3_5
3A
P3_6
4A
RxD
OE#
: Optional
UART connector (J3)
1B2
2B1
SCK3
SCK
2B2
3B1
TxD3
TxD
3B2
4B1
RxD3
RxD
5V
4B2
MUX
Note: Letters in Red indicate
functions in use.
MUX
S
OE#
3.3V
S
3.3V
DIP
SW2-1
DIP
SW14-7
UART Interface Block Diagram
SW2-1 (DIP Switch for RTK772100BC00000BR System Setting) Function Setting
Function
DIP Switch
ON
SW2-1
To IrDA module
Serial/CD select (U2)
1B1
1A
P3_5 / ET_RXER / SSIWS1 /
SCI_TXD0 / TxD3
Table2.7.1
I/O
JP5
P3_4 / ET_RXCLK / SSISCK1 /
SCI_SCK0 / SCK3
Figure 2.7.1
JP1
OFF
Use P3_[6:3] and P2_[11:0] as Ethernet PHY
Use P3_[6:3] and P2_[11:0] as MOST control pin
control pin (initial setting)
and expansion connector pin
indicates setting function.
Table2.7.2
SW14-7 (DIP Switch for System Setting) Function Setting
Function
DIP Switch
ON
SW14-7
Use P3_[6:3] as SCI pin (initial setting)
OFF
Use P3_[6:3] as SSIF pin
indicates setting function.
Table2.7.3
JP1 and JP5 Function Settings
Short
Jumper
JP1
Use SCI in smart card interface mode
Open
Use SCI in serial communication interface mode
(initial setting)
JP5
Connect RxD3 pin to IrDA module
Do not connect RxD3 pin to IrDA module
(initial setting)
indicates setting function.
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
2-21
R7S72100 CPU (GENMAI) Optional Board
2.8
RTK7721000B00000BR
2.
Functional Specification
Audio Interface
The RTK7721000B00000BR has two audio DACs (AK4353, Asahi Kasei Microdevices) as the audio interface. The I2C
bus interface (RIIC) channel 2 and the on-chip serial sound interface with FIFO (SSIF) channel 3 and 4 execute the register
control for AK4353 and the output control of sound data respectively. The P4_14 pin executes the PDN control.
Figure 2.8.1 shows the Audio Interface Block Diagram.
2
3
To EEPROM
To MOST I/F connector
To SD card slot
Expansion
connector
10
3.3V
4
To LCD panel I/F2
Audio DAC1
AK4353 (U6)
R7S72100 (U1)
3.3V
P1_4 / SCL2
SCL2
P4_14
PDN#
P1_5 / SDA2 / DV1_CLK
P1_5
XOUT
MCKI
P4_12 / LCD1_CLK /
SD_CLK_0 / SSISCK3
SSISCK3
SSISCK3
BICK
P4_13 / LCD1_TCON0 /
SD_CMD_0 / SSIWS3
SSIWS3
SSIWS3
P4_15 / LCD1_TCON2 /
SD_D2_0 / SSITxD3
SSITxD3
SSITxD3
P11_4 / DV0_DATA16 /
SSISCK4 / LCD0_DATA3
SSISCK4
P11_5 / DV0_DATA17 /
SSIWS4 / LCD0_DATA2
SSIWS4
P11_6 / DV0_DATA18 /
SSIDATA4 / LCD0_DATA1
SSIDATA4
P4_14 / LCD1_TCON1 / SD_D3_0
CLK
CLK3
0.1µF
220Ω
SCL/CCLK
27kΩ
P4_14
CAD0
CAD1
J6
10µF
AOUTR
+
SDA/CDTI
220Ω
27kΩ
Chip address [3]
Audio DAC2
AK4353 (U7)
XOUT
PDN#
: Optional
MCKI
SSISCK4
BICK
SSIWS4
LRCK
VCOM
3.3V
SSIDATA4
To LCD panel I/F1
To DV input I/F1
0.1µF
SDTI
3
AOUTL
To DV input I/F2
10µF
220Ω
SCL/CCLK
27kΩ
3.3V
SDA2
SDA/CDTI
CAD0
CAD1
Chip address [1]
J9
10µF
AOUTR
+
P1_5
+
10µF
I2C
CSN
SCL2
220Ω
27kΩ
Audio Interface Block Diagram
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
10µF
+
AOUTL
3.3V 3.3V
Note: Letters in Red indicate
functions in use.
Figure 2.8.1
+
10µF
I2C
CSN
Clock Buffer
(U16)
REF
VCOM
SDTI
+
22.5792MHz
(X8)
LRCK
3.3V
2-22
R7S72100 CPU (GENMAI) Optional Board
2.9
RTK7721000B00000BR
2.
Functional Specification
CD Deck Interface
RTK7721000B00000BR has a CD deck interface connector which is controlled by the on-chip serial sound interface with
FIFO (SSIF) channel 1 embedded in the R7S72100, the Renesas serial peripheral interface (RSPI) channel 4, and the
general I/O ports. The RSPI pin is also used in the audio CODEC (WM8978) control on the RTK7721000B00000BR. The
select signal should be output at the port P3_3 when accessing to the DC deck interface.
Figure 2.9.1 shows the CD Deck Interface Block Diagram. Table2.9.1 lists the SW2-1 (DIP Switch for
RTK772100BC00000BR System Setting) Function Setting,
Table2.9.2 lists the SW14-7 (DIP Switch for System Setting) Function Setting, and Table2.9.3 lists the
RTK772100BC00000BR JP3 Function Setting.
4
3
2
To LAN I/F
To NAND flash memory
To MMC card slot
4
To audio CODEC
Expansion
connector
To IrDA module
To SIM card slot
To UART connector
11
LAN/Option select (U14)
R7S72100 (U1)
P3_3 / ET_MDIO
1A
P3_4 / ET_RXCLK / SSISCK1 /
SCI_SCK0 / SCK3
2A
P3_5 / ET_RXER / SSIWS1 /
SCI_TXD0 / TxD3
3A
P3_6 / ET_RXDV / SSIRxD1 /
SCI_RXD0 / RxD3
4A
1B1
1B2
2B1
P3_3
2B2
3B1
P3_4
3B2
4B1
P3_5
4B2
P3_6
P3_3
1A
P3_4
2A
P3_5
3A
P3_6
4A
3.3V
1B1
1B2
2B1
MUX
OE#
CD deck connector (J8)
IMSA-9617S-22
Serial/CD select (U2)
2B2
3B1
SSISCK1
3B2
4B1
SSIWS1
4B2
SSIRxD1
IIS_BCK
IIS_LRCK
IIS_DATA
MUX
S
OE#
3.3V
S
3.3V
3.3V
DIP
SW2-1
DIP
SW14-7
P4_0 / FRE / RSPCK4 / MMC_D4
RSPCK4
P4_2 / FALE / MOSI4 / MMC_D6
MOSI4
P4_3 / FWE / MISO4 / MMC_D7
MISO4
MOSI4
RES
MISO4
3.3V
RSPCK4
CDCK
3.3V
RES#
CDFS
CDSI
CDSO
3.3V
P1_12
P1_12
RES
P1_13
P1_13
P1_13
CDRST
8V
3.3V
FLAG6
DC8V
P1_12
TRANS
P3.3V
IRQ6
BLKCK
GND
JP3
2
P3_1 / IRQ6 / AUDIO_CLK
3
1
To IRQ input switch (SW6)
Note: Letters in Red indicate
functions in use.
: Optional
Figure 2.9.1
Table2.9.1
To HCI connector
CD Deck Interface Block Diagram
SW2-1 (DIP Switch for RTK772100BC00000BR System Setting) Function Setting
Function
DIP Switch
ON
SW2-1
3.3V
3.3V
IRQ6
OFF
Use P3_[6:3] and P2_[11:0] as Ethernet PHY
Use P3_[6:3] and P2_[11:0] as MOST control pin
control pin (intial setting)
and expansion connector pin
indicates setting function.
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
2-23
R7S72100 CPU (GENMAI) Optional Board
Table2.9.2
RTK7721000B00000BR
Functional Specification
SW14-7 (DIP Switch for System Setting) Function Setting
Function
DIP Switch
ON
SW14-7
2.
Use P3_[6:3] as SCI pin (initial setting)
OFF
Use P3_[6:3] as SSIF pin
indicates setting function.
Table2.9.3
RTK772100BC00000BR JP3 Function Setting
1-2
Jumper
JP3
2-3
Use P3_1 as IRQ6 input pin from SW6 on
Use P3_1 as IRQ6 input pin from CD deck
RTK772100BC00000BR (initial setting)
interface
indicates setting function.
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
2-24
R7S72100 CPU (GENMAI) Optional Board
2.10
RTK7721000B00000BR
2.
Functional Specification
HCI Module Interface
The RTK7721000B00000BR has a HCI module interface connector which is connected with the R7S72100 on-chip serial
communication interface with FIFO (SCIF) channel 7, on-chip serial sound interface with FIFO (SSIF) channel 5, and the
I2C bus interface (RIIC) channel 0.
Figure 2.10.1 shows the HCI Module Interface Block Diagram. Table2.10.1 lists the SW2-1 (DIP Switch for
RTK772100BC00000BR System Setting) Function Setting, and Table2.10.2 lists the RTK772100BC00000BR JP3
Function Setting.
4
2
4
To SDRAM
To LAN I/F
Expansion
connector
To NOR flash memory
13
IRQ6
To CD deck connector
LAN/Option select (U12)
R7S72100 (U1)
P2_4 / ET_TXD0 / SSISCK5
1A
P2_5 / ET_TXD1 / SSIWS5
2A
P2_6 / ET_TXD2 / SSIRxD5
3A
P2_7 / ET_TXD3 / SSITxD5
4A
1B2
2B1
SSISCK5
2B2
3B1
SSIWS5
3B2
4B1
SSIRxD5
4B2
SSITxD5
MUX
TxD7
P7_4 / CKE / TxD7
HCI connector(J7)
1B1
OE#
3.3V
CTS7
P7_6 / WE0/DQMLL / CTS7
AUDIO_XOUT
P3_1
AUDIO_CLK
SSISCK5
SSISCK
SSIWS5
SSIWS
SSITxD5
SSITxD
SSIRxD5
SSIRxD
TxD7
TxD
RxD7
RxD
CTS7
CTS
S
RxD7
P7_5 / RD/WR / RxD7
XOUT
3.3V
RTS7
P7_7 / WE1/WE/DQMLU / RTS7
3.3V
SCL0
P1_1 / SDA0
SDA0
RTS7
RTS
P7_8
SCL0
SCL
SDA0
SDA
P7_8
PORT
P7_8 / RD
P3_1 / IRQ6 / AUDIO_CLK
22.5792MHz
(X8)
CLK
DIP
SW2-1
P1_0 / SCL0
JP3
2
3
1
P3_1
To IRQ input switch (SW6)
Clock Buffer
(U16)
REF
CLK3
5V
3.3V
XOUT
Note: Letters in Red indicate
functions in use.
: Optinal
Figure 2.10.1
Table2.10.1
HCI Module Interface Block Diagram
SW2-1 (DIP Switch for RTK772100BC00000BR System Setting) Function Setting
Function
DIP Switch
ON
SW2-1
OFF
Use P3_[6:3] and P2_[11:0] as Ethernet PHY
Use P3_[6:3] and P2_[11:0] as MOST control pin
control pin (initial setting)
and expansion connector pin
indicates setting function.
Table2.10.2
RTK772100BC00000BR JP3 Function Setting
1-2
Jumper
JP3
2-3
Use P3_1 as IRQ6 input pin from SW6 on
Use P3_1 as AUDIO_CLK input pin from HCI
RTK772100BC00000BR (initial setting)
module interface
indicates setting function.
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
2-25
R7S72100 CPU (GENMAI) Optional Board
2.11
RTK7721000B00000BR
2.
Functional Specification
LCD Panel Output Interface
The RTK7721000B00000BR has 5 connectors with 3 types for the LCD panel connection. The video display controller 5
(VDC5) embedded in the R7S72100 controls the LCD panel.
An oscillator should be mounted to X9 on the RTK772100BC00000BR when using P3_7 as the LCD1_EXTCLK input pin,
and to X1 when using P5_8 as the LCD0_EXTCLK pin.
The LVDS termination resistor (R315 to R318) or RL0 to RL7 (R14, R16, R17, R20, R22, R24, R26 and R29) on the
RTK772100BC00000BR should be removed because the signals from LCD1_DATA0 to LCD1_DATA7 may be affected
when the LCD panel output interface is used.
Table2.11.1 lists the RTK772100BC00000BR JP6 Function Setting. Figure 2.11.1 and Figure 2.11.2 show the LCD Panel
Output Interface Block Diagram. Table2.11.2 lists the SW2-1 (DIP Switch for RTK772100BC00000BR System Setting)
Function Setting, Table2.11.3 lists the RTK772100BC00000BR JP4 Function Setting, and Table2.11.4 lists the JP6, JP7,
JP2 and JP3 Function Settings.
Table2.11.1
RTK772100BC00000BR JP6 Function Setting
1-2
Jumper
JP6
2-3
Use P3_7 as LCD1_EXTCLK input pin
Use P3_7 as CS1 output pin (initial setting)
indicates setting function.
2
22
Expansion
connector
35
R7S72100 (U1)
29
To HCI I/F
To CMOS camera I/F
To DV input I/F1
LCD output connector 1-1
(J10)
3.3V
3
To audio DAC2
P10_0 / DV0_CLK /
LCD0_DATA23 / VIO_CLK
P10_0
P11_15
LCD0_CLK
P10_1 / DV0_VSYNC /
LCD0_DATA22 / VIO_VD
P10_1
P11_10
LCD0_TCON4
P10_2 / DV0_HSYNC /
LCD0_DATA21 / VIO_HD
P10_2
P11_11
LCD0_TCON3
HSYNC
P10_3 / LCD0_DATA20 /
VIO_FLD
P10_3
P11_12
LCD0_TCON2
DE
P10_[15:4] / DV0_DATA[11:0] /
LCD0_DATA[8:19] / VIO_D[11:0]
P10_[15:4]
P11_13
LCD0_TCON1
INT
P11_[3:0] / DV0_DATA[15:12] /
LCD0_DATA[4:7] / VIO_D[15:12]
P11_[3:0]
P11_14
LCD0_TCON0
RESET
P11_4 / DV0_DATA16 /
SSISCK4 / LCD0_DATA3
P11_4
P10_[6:7]
LCD0_DATA[17:16]
R[5:4]
P11_5 / DV0_DATA17 /
SSIWS4 / LCD0_DATA2
P11_5
P10_[8:11]
LCD0_DATA[15:12]
R[3:0]
P11_6 / DV0_DATA18 /
SSIDATA4 / LCD0_DATA1
P11_6
P10_[12:15]
LCD0_DATA[11:8]
G[5:2]
P11_7 / DV0_DATA19 /
LCD0_DATA0
P11_7
P11_[0:1]
LCD0_DATA[7:6]
G[1:0]
P11_[11:8] / DV0_DATA[23:20] /
LCD0_TCON[3:6]
P11_[11:8]
P11_[2:3]
LCD0_DATA[5:4]
B[5:4]
P11_[14:12] / LCD0_TCON[2:0]
P11_[14:12]
LCDCLK
VSYNC
3.3V
LCD0_DATA0
P11_7
LCD-KIT-B01
RGB666
B0
5V
3.3V
P11_15
P11_15 / LCD0_CLK
P11_[4:6]
LCD0_DATA[3:1]
B[3:1]
3.3V
3.3V
P1_0 / SCL0
P1_0
P1_0
SCL0
SCL
P1_1 / SDA0
P1_1
P1_1
SDA0
SDA
P5_8 / CS2 / LCD0_EXTCLK
P5_8
To SDRAM1
P3_7 / LCD1_EXTCLK / CS1
2
3
1
JP6
3.3V
LCD output connector 1-2
(J11)
To NOR flash memory 2
CLK Socket (X9)
LCD0_CLK
Note: Letters in Red indicate
functions in use.
: Optional
LCD0_TCON[6:0]
P10_[0:5]
LCD0_DATA[23:16]
R[7:0]
LCD0_DATA[15:8]
G[7:0]
LCD0_DATA[7:0]
B[7:0]
P5_8
Figure 2.11.1
LCD0_EXTCLK
Socket (X1)
CLK
TCON[6:0]
MIL connector
RGB888
5V
3.3V
LCD Panel Output Interface (ch0) Block Diagram
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
CLK
P11_[8:9]
2-26
R7S72100 CPU (GENMAI) Optional Board
4
RTK7721000B00000BR
10
To serial flash memory 2
8
3
To SD card slot
6
1
JP3
2
P2_[11:10]
P2_9
To serial flash memory 1
8
2.
To LVDS panel I/F
Expansion connector
4
3
1
Functional Specification
To DV input I/F2
To LIN transceiver
To audio DAC (PDN#)
To IEBus transceiver
To audio DAC1
3.3V
3.3V
35
R7S72100 (U1)
LCD output connector 2-1
(J12)
2 JP2
3.3V
P1_6 / SCL3 / DV1_VSYNC
P1_6
P4_12
LCD1_CLK
P1_7 / SDA3 / DV1_HSYNC
P1_7
P4_15
LCD1_TCON2
VSYNC
P2_[15:12] / SPBIO[3:0]1_0 /
LCD1_DATA[15:12]
P2_[15:12]
P4_13
LCD1_TCON0
HSYNC
P4_[15:14] / LCD1_TCON[2:1] /
SD_D[2:3]_0
P4_[15:14]
P4_14
LCD1_TCON1
DE
P4_13 / LCD1_TCON0 /
SD_CMD_0 / SSIWS3
P4_13
P4_8
P4_8
INT
P4_12 / LCD1_CLK /
SD_CLK_0 / SSISCK3
P4_12
P4_9
P4_9
P4_[11:10] / LCD1_TCON[6:5] /
SD_D[0:1]_0
P4_[11:10]
RESET
R5
R4
R[3:0]
P4_9 / LCD1_TCON4 / SD_WP_0
P4_9
P4_8 / LCD1_TCON3 / SD_CD_0
P4_8
P9_2 / LCD1_DATA18 /
SPBCLK_0
P9_2
P9_3 / LCD1_DATA19 /
SPBSSL_0
P9_3
P9_[4:7] / LCD1_DATA[20:23] /
SPBIO[0:3]0_0
P9_[4:7]
P5_10
P5_9
P2_[15:12]
P2_[11:9]
P2_8
P5_[7:6]
LCD1_DATA[11:9]
LCD1_DATA8
LCD1_DATA[7:6]
G[5:3]
G2
G[1:0]
P5_[5:0]
LCD1_DATA[5:0]
B[5:0]
SCL
SDA
SCL3
SDA3
3.3V
LCD-KIT-B01
RGB666
5V
3.3V
LCD output connector 2-2
(J14)
P5_0
P5_0 / TXCLKOUTP /
LCD1_DATA0 / DV1_DATA0
RE0
RL0
P5_1 / TXCLKOUTM /
LCD1_DATA1 / DV1_DATA1
RE1
RL1
P5_2 / TXOUT2P /
LCD1_DATA2 / DV1_DATA2
RE2
RL2
P5_3 / TXOUT2M /
LCD1_DATA3 / DV1_DATA3
RE3
RL3
P5_4 / TXOUT1P /
LCD1_DATA4 / DV1_DATA4
RE4
RL4
P5_5 / TXOUT1M / FCE /
LCD1_DATA5 / DV1_DATA5
RE5
RL5
P5_6 / TXOUT0P /
LCD1_DATA6 / DV1_DATA6
RE6
RL6
P5_7 / TXOUT0M /
LCD1_DATA7 / DV1_DATA7
RE7
RL7
LCD1_CLK
LCDDCK
P5_1
LCD1_TCON3
LCDVSYN
LCD1_TCON4
LCDHSYN
LCD1_TCON5
LCDDISP
P5_2
P5_3
P4_10
3.3V
P5_4
P4_11
LCD1_TCON6
TP_IRQ#
3.3V
P5_5
To NAND
BKPWM
R0P7724LE0011RL
RGB888
P5_6
LCDDON
P5_7
2
P5_9
P5_9 / ET_MDC / CRx1 / IERxD /
LCD1_DATA16
JP4
2
1
3
4
LAN/Option select (U13)
1A
P2_9 / ET_RXD1 / LRXD0 /
LCD1_DATA9
2A
P2_10 / ET_RXD2 / LTXD0 /
LCD1_DATA10
3A
P2_11 / ET_RXD3 /
LCD1_DATA11
4A
SDA0
LCD1_DATA[23:16]
R[7:0]
LCD1_DATA[15:8]
G[7:0]
LCD1_DATA[7:0]
B[7:0]
5V
JP6
1B2
2B1
P2_8
2B2
3B1
P2_9
3B2
4B1
P2_10
4B2
P2_11
LCD output connector 2-3
(J13)
3.3V
LCD1_CLK
3.3V
LCD1_TCON[6:0]
CLK
TCON[6:0]
S
DIP
SW2-1
P5_8
P5_8 / CS2 / LCD0_EXTCLK
3.3V
To LAN I/F
1B1
OE#
To SDRAM1
3
1
JP6
P9_[7:3]
P9_2
MUX
2
SCL0
To CAN I/F
To Ethernet PHY
P5_10
P2_8 / ET_RXD0 / LCD1_DATA8
SCL3
SDA3
P1_6
P1_7
P5_10 / CTx1 / IETxD /
LCD1_DATA17
P3_7 / LCD1_EXTCLK / CS1
LCD1_DATA17
LCD1_DATA16
LCD1_DATA[15:12]
JP7
LCDCLK
To NOR flash memory 2
CLK Socket (X9)
P5_8
Note: Letters in Red indicate
functions in use.
LCD1_DATA[23:16]
R[7:0]
LCD1_DATA[15:8]
G[7:0]
LCD1_DATA[7:0]
B[7:0]
5V
MIL connector
RGB888
3.3V
Socket (X1)
LCD0_EXTCLK
CLK
: Optional
Figure 2.11.2
Table2.11.2
LCD Panel Output Interface (ch1) Block Diagram
SW2-1 (DIP Switch for RTK772100BC00000BR System Setting) Function Setting
Function
DIP Switch
ON
SW2-1
OFF
Use P3_[6:3] and P2_[11:0] as Ethernet PHY
Use P3_[6:3] and P2_[11:0] as MOST control pin
control pin (initial setting)
and expansion connector pin
indicates setting function.
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
2-27
R7S72100 CPU (GENMAI) Optional Board
Table2.11.3
2.
Functional Specification
RTK772100BC00000BR JP4 Function Setting
1-2
Jumper
JP4
RTK7721000B00000BR
2-3
Use P5_9 as CRx1 input pin
None
Use P5_9 as ET_MDC output
Use P5_9 as IERxD input pin or
pin (initial setting)
LCD1_DATA16 output pin
indicates setting function.
Table2.11.4
JP6, JP7, JP2 and JP3 Function Settings
1-2
Jumper
JP6
Use P9_2 as LCD1_DATA18 output pin
JP7
Use P5_9 as IERxD input pin or
JP2
Use P5_9 as IERxD input pin
JP3
Use P2_9 as LRXD0 input pin
2-3 or Open
Use P9_2 as SPBCLK_0 output pin
(initial setting)
Use P5_9 as ET_MDC output pin (initial setting)
LCD1_DATA16 output pin
Use P5_9 as LCD1_DATA16 output pin
(initial setting)
Use P2_9 as LCD1_DATA9 output pin
(initial setting)
indicates setting function.
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
2-28
R7S72100 CPU (GENMAI) Optional Board
2.12
RTK7721000B00000BR
2.
Functional Specification
Analog RGB Output Interface
The RTK7721000B00000BR includes video DACs and converts the LCD panel control signal to the analog RBG. The
signal of the converted analog RGB is output from the D-sub 15-pin connector.
The oscillator should be mounted to X9 the RTK772100BC00000BR when using P3_7 as the LCD1_EXTCLK input pin,
and to X1 when using P5_8 as the LCD0_EXTCLK pin.
The LVDS termination resistors (R315 to R318) or RL0 o RL7 (R14, R16, R17, R20, R22, R24, R26 and R29) on the
RTK772100BC00000BR should be removed because the signals from LCD1_DATA0 to LCD1_DATA7 may be affected
when the analog RGB output interface (ch1) is used.
Table2.12.1 lists the RTK772100BC00000BR JP6 Function Setting. Figure 2.12.1 and Figure 2.12.2 show the Analog RGB
Output Interface Block Diagram. Table2.12.2 lists the SW2-1 (DIP Switch for RTK772100BC00000BR System Setting)
Function Setting, Table2.12.3 lists the RTK772100BC00000BR JP4 Function Setting, and Table2.12.4 lists the JP6, JP7,
JP2 and JP3 Function Settings.
Table2.12.1
RTK772100BC00000BR JP6 Function Setting
1-2
Jumper
JP6
2-3
Use P3_7 as LCD1_EXTCLK input pin
Use P3_7 as CS1 output pin (initial setting)
indicates setting function.
3
To audio DAC2
25
35
R7S72100 (U1)
20
Analog RGB connector 1
(J15)
D-sub15
Video DAC1
ADV7123 (U8)
P10_0 / DV0_CLK /
LCD0_DATA23 / VIO_CLK
P10_0
P10_[0:7]
P10_1 / DV0_VSYNC /
LCD0_DATA22 / VIO_VD
P10_1
P10_2 / DV0_HSYNC /
LCD0_DATA21 / VIO_HD
P10_2
P10_3 / LCD0_DATA20 /
VIO_FLD
P10_3
P10_[15:4] / DV0_DATA[11:0] /
LCD0_DATA[8:19] / VIO_D[11:0]
P10_[15:4]
P11_[3:0] / DV0_DATA[15:12] /
LCD0_DATA[4:7] / VIO_D[15:12]
P11_[3:0]
P11_4 / DV0_DATA16 /
SSISCK4 / LCD0_DATA3
P11_4
P11_5 / DV0_DATA17 /
SSIWS4 / LCD0_DATA2
P11_5
1
P11_6 / DV0_DATA18 /
SSIDATA4 / LCD0_DATA1
P11_6
2
SYNC
P11_7 / DV0_DATA19 /
LCD0_DATA0
P11_7
3
PSAVE
P11_[14:12] / LCD0_TCON[2:0]
P11_[14:12]
P11_15 / LCD0_CLK
P11_15
P11_13
P5_8 / CS2 / LCD0_EXTCLK
P5_8
P11_14
P3_7 / LCD1_EXTCLK / CS1
To DV input I/F1
To CMOS camera I/F
P11_[3:0]
P11_[6:4]
Expansion connector
Other than P10_3
To SDRAM1
LCD0_DATA[23:16]
R[9:2]
IOR
P10_[8:15]
LCD0_DATA[15:8]
G[9:2]
IOG
P11_[0:7]
LCD0_DATA[7:0]
B[9:2]
IOB
Green
75Ω
3.3V
3.3V
Red
75Ω
75Ω
3.3V
Blue
LCD0_TCON1
VSYNC
LCD0_TCON0
HSYNC
Clock Buffer (U9)
P11_15
LCD0_CLK
REF CLKOUT
CLOCK
3.3V
SW14
3.3V
BLANK
3.3V
2
3
1
JP6
To NOR flash memory 2
CLK Socket (X9)
P5_8
LCD0_EXTCLK
Socket (X1)
CLK
Note: Letters in Red indicate
functions in use.
: Optional
Figure 2.12.1
Analog RGB Output Interface (ch0) Block Diagram
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
2-29
R7S72100 CPU (GENMAI) Optional Board
3
RTK7721000B00000BR
2.
Functional Specification
To SD card slot
6
2
To serial flash memory 1
4
2
To serial flash memory 2
8
3
To LVDS panel I/F
1
P4_12 / LCD1_CLK /
SD_CLK_0 / SSISCK3
P4_12
P4_14 / LCD1_TCON1 / SD_D3_0
P4_14
2 JP2
P5_9
P5_10
28
R7S72100 (U1)
3
8
To audio DAC
To LIN I/F
To DV input I/F2
P2_[11:10]
P2_9
Expansion connector
JP3
To IEBus I/F
P9_[7:3], P5_10
P5_9
JP7
P9_2
JP6
P2_[15:8]
Analog RGB connector 2
(J16)
D-sub15
Video DAC2
ADV7123 (U10)
LCD1_DATA[23:16]
R[9:2]
IOR
LCD1_DATA[15:8]
G[9:2]
IOG
P4_10 / LCD1_TCON5 / SD_D1_0
P4_10
P9_2 / LCD1_DATA18 /
SPBCLK_0
P9_2
P9_3 / LCD1_DATA19 /
SPBSSL_0
P9_3
P9_[7:4] / LCD1_DATA[23:20] /
SPBIO[3:0]0_0
P9_[4:7]
P2_[15:12] / SPBIO[3:0]1_0 /
LCD1_DATA[15:12]
P2_[15:12]
P5_[7:0]
LCD1_DATA[7:0]
B[9:2]
3.3V
Red
75Ω
Green
75Ω
3.3V
IOB
75Ω
3.3V
Blue
LCD1_TCON1
VSYNC
LCD1_TCON5
HSYNC
Clock Buffer (U11)
P4_12
LCD1_CLK
REF CLKOUT
CLOCK
3.3V
SW14
3.3V
P5_0
P5_0 / TXCLKOUTP /
LCD1_DATA0 / DV1_DATA0
RE0
RL0
P5_1 / TXCLKOUTM /
LCD1_DATA1 / DV1_DATA1
RE1
RL1
P5_2 / TXOUT2P /
LCD1_DATA2 / DV1_DATA2
RE2
RL2
P5_3 / TXOUT2M /
LCD1_DATA3 / DV1_DATA3
RE3
RL3
P5_4 / TXOUT1P /
LCD1_DATA4 / DV1_DATA4
RE4
RL4
P5_5 / TXOUT1M / FCE /
LCD1_DATA5 / DV1_DATA5
RE5
RL5
P5_6 / TXOUT0P /
LCD1_DATA6 / DV1_DATA6
RE6
RL6
4
BLANK
3.3V
P5_1
5
SYNC
6
PSAVE
P5_2
P5_3
P5_4
P4_14
P5_5
To NAND
P4_10
P5_6
P5_8
P5_7
P5_7 / TXOUT0M /
LCD1_DATA7 / DV1_DATA7
2
RE7
RL7
LCD0_EXTCLK
Socket (X1)
CLK
To CAN transceiver
P5_9
P5_9 / ET_MDC / CRx1 / IERxD /
LCD1_DATA16
JP4
2
1
3
To LAN I/F
P5_10 / CTx1 / IETxD /
LCD1_DATA17
P5_10
4
LAN/Option select (U13)
P2_8 / ET_RXD0 / LCD1_DATA8
1A
P2_9 / ET_RXD1 / LRXD0 /
LCD1_DATA9
2A
P2_10 / ET_RXD2 / LTXD0 /
LCD1_DATA10
3A
P2_11 / ET_RXD3 /
LCD1_DATA11
4A
1B2
2B1
P2_8
2B2
3B1
P2_9
3B2
4B1
P2_10
4B2
P2_11
3.3V
MUX
OE#
S
P5_8
P5_8 / CS2 / LCD0_EXTCLK
To SDRAM1
2
P3_7 / LCD1_EXTCLK / CS1
3
1
JP6
To LAN I/F
1B1
DIP
SW2-1
To NOR flash memory 2
Socket (X9)
CLK
Note: Letters in Red indicate
functions in use.
: Optional
Figure 2.12.2
Table2.12.2
Analog RGB Output Interface (ch1) Block Diagram
SW2-1 (DIP Switch for RTK772100BC00000BR System Setting) Function Setting
Function
DIP Switch
ON
SW2-1
OFF
Use P3_[6:3] and P2_[11:0] as Ethernet PHY
Use P3_[6:3] and P2_[11:0] as MOST control pin
control pin (initial setting)
and expansion connector pin
indicates setting function.
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
2-30
R7S72100 CPU (GENMAI) Optional Board
Table2.12.3
2.
Functional Specification
RTK772100BC00000BR JP4 Function Setting
1-2
Jumper
JP4
RTK7721000B00000BR
2-3
Use P5_9 as CRx1 input pin
None
Use P5_9 as ET_MDC output
Use P5_9 as IERxD input pin or
pin (initial setting)
LCD1_DATA16 output pin
indicates setting function.
Table2.12.4
JP6, JP7, JP2 and JP3 Function Settings
1-2
Jumper
JP6
Use P9_2 as LCD1_DATA18 output pin
JP7
Use P5_9 as IERxD input pin or
JP2
Use P5_9 as IERxD input pin
JP3
Use P2_9 as LRXD0 input pin
2-3 or Open
Use P9_2 as SPBCLK_0 output pin
(initial setting)
Use P5_9 as ET_MDC output pin (initial setting)
LCD1_DATA16 output pin
Use P5_9 as LCD1_DATA16 output pin
(initial setting)
Use P2_9 as LCD1_DATA9 output pin
(initial setting)
indicates setting function.
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
2-31
R7S72100 CPU (GENMAI) Optional Board
2.13
RTK7721000B00000BR
2.
Functional Specification
Digital Video Signal Input Interface
The R7S72100 has digital video signal input pins (DV pins) respond to the YCbCr422, YCbCr444, RGB888, RGB666 and
RGB565 images. The RTK7721000B00000BR connects the R7S72100 DV pins to the general MIL connectors.
The LVDS termination resistors (R315 to R318) or RL0 to RL7 (R14, R16, R17, R20, R22, R24, R26 and R29) should be
removed because the signals from DV1_DATA0 to DV1_DATA7 may be affected when the digital video signal input
interface (ch1) is used.
Figure 2.13.1 shows the Digital Video Signal Input Interface Block Diagram.
19
Expansion
connector
27
To CMOS camera I/F
To LCD panel I/F1
20
R7S72100 (U1)
DV input connector 1 (J18)
P10_0 / DV0_CLK /
LCD0_DATA23 / VIO_CLK
P10_0
P10_0
DV0_CLK
P10_1 / DV0_VSYNC /
LCD0_DATA22 / VIO_VD
P10_1
P10_1
DV0_VSYNC
P10_2 / DV0_HSYNC /
LCD0_DATA21 / VIO_HD
P10_2
P10_2
DV0_HSYNC
P10_[15:4] / DV0_DATA[11:0] /
LCD0_DATA[8:19] / VIO_D[11:0]
P10_[15:4]
P10_[15:4]
DV0_DATA[11:0]
P11_[3:0] / DV0_DATA[15:12] /
LCD0_DATA[4:7] / VIO_D[15:12]
P11_[3:0]
P11_[3:0]
DV0_DATA[15:12]
P11_4 / DV0_DATA16 /
SSISCK4 / LCD0_DATA3
P11_4
P11_[11:7]
DV0_DATA[23:19]
P11_5 / DV0_DATA17 /
SSIWS4 / LCD0_DATA2
P11_5
P11_[6:4]
DV0_DATA[18:16]
P11_6 / DV0_DATA18 /
SSIDATA4 / LCD0_DATA1
P11_6
P11_7 / DV0_DATA19 /
LCD0_DATA0
P11_7
P11_[11:8] / DV0_DATA[23:20] /
LCD0_TCON[3:6]
P11_[11:8]
3
5V
3.3V
To audio DAC2
10
To LCD panel I/F2
3.3V
1
3.3V
P1_5
P1_5 / SDA2 / DV1_CLK
3.3V
To EEPROM
To MOST I/F
connecor
To audio DAC
DV input connector 2 (J19)
P1_6 / SCL3 / DV1_VSYNC
P1_6
P1_5
DV1_CLK
P1_7 / SDA3 / DV1_HSYNC
P1_7
P1_6
DV1_VSYNC
P1_7
DV1_HSYNC
P5_[7:0]
DV1_DATA[7:0]
P5_0 / TXCLKOUTP /
LCD1_DATA0 / DV1_DATA0
RL0
RE0
P5_1 / TXCLKOUTM /
LCD1_DATA1 / DV1_DATA1
RL1
RE1
P5_1
P5_2 / TXOUT2P /
LCD1_DATA2 / DV1_DATA2
RL2
RE2
P5_2
P5_3 / TXOUT2M /
LCD1_DATA3 / DV1_DATA3
RL3
RE3
P5_3
P5_4 / TXOUT1P /
LCD1_DATA4 / DV1_DATA4
RL4
RE4
P5_4
P5_5 / TXOUT1M / FCE /
LCD1_DATA5 / DV1_DATA5
RL5
RE5
P5_5
P5_6 / TXOUT0P /
LCD1_DATA6 / DV1_DATA6
RL6
RE6
P5_6
P5_7 / TXOUT0M /
LCD1_DATA7 / DV1_DATA7
RL7
RE7
P5_7
Note: Letters in Red indicate
functions in use.
P5_0
8
5V
3.3V
To NAND flash memory
To LVDS panel I/F
: Optional
Figure 2.13.1
Digital Video Signal Input Interface Block Diagram
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
2-32
R7S72100 CPU (GENMAI) Optional Board
2.14
RTK7721000B00000BR
2.
Functional Specification
CMOS Camera Input Interface
The R7S72100 includes a capture module capture engine unit (CEU) which imports video data input from outside and
transfers the data to the memory. The RTK7721000B00000BR connects the R7S72100 CEU pin to the CMOS camera
connector (MT9V024IA7XTCD ES, Aptina) and the connectable 26-pin MIL pitch connector.
Figure 2.14.1 shows the CMOS Camera Input Interface Block Diagram, Table2.14.1 lists the JP4 Function Setting.
2
To HCI I/F
19
Expansion
connector
To DV input I/F1
22
To LCD panel I/F1
23
R7S72100 (U1)
CMOS camera connector (J17)
P10_0 / DV0_CLK /
LCD0_DATA23 / VIO_CLK
P10_0
P10_0
VIO_CLK
P10_1 / DV0_VSYNC /
LCD0_DATA22 / VIO_VD
P10_1
P10_1
VIO_VD
S_FV (Frame Valid)
P10_2 / DV0_HSYNC /
LCD0_DATA21 / VIO_HD
P10_2
P10_2
VIO_HD
S_LV (Line Valid)
P10_3 / LCD0_DATA20 /
VIO_FLD
P10_3
P10_[13:6]
VIO_D[9:2]
P10_[15:4] / DV0_DATA[11:0] /
LCD0_DATA[8:19] / VIO_D[11:0]
P10_[15:4]
P10_[5:4]
VIO_D[1:0]
S_PIXCLK
S_DOUT[7:0]
3.3V
S_DOUTLSB[1:0]
P10_3
RES
3
1
P11_[3:0]
P1_0 / SCL0
SCL0
SCL0
DEMO_SCL
SDA0
SDA0
DEMO_SDA
2
DEMO_RST
3.3V
P1_1 / SDA0
RES#
5V
JP4
3.3V
P11_[3:0] / DV0_DATA[15:12] /
LCD0_DATA[4:7] / VIO_D[15:12]
RES
P10_[15:14]
VIO_D[11:10]
NC
P11_[3:0]
VIO_D[15:12]
NC
XMCLK
Socket (X2)
CLK
27MHz
Note: Letters in Red indicate
functions in use.
: Optional
Figure 2.14.1
Table2.14.1
CMOS Camera Input Interface Block Diagram
JP4 Function Setting
1-2
Jumper
JP4
2-3
Execute reset control for CMOS camera using
Execute reset control for CMOS camera with
RES singal generaged by the
P10_3 pin (initial setting)
RTK7721000B00000BR
indicates setting function.
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
2-33
R7S72100 CPU (GENMAI) Optional Board
2.15
RTK7721000B00000BR
2.
Functional Specification
Key Input Switch
The ports from P1_8 to P1_11 can be used as the key input switches via the A/D converter (ADC) by setting to the analog
input pins (AN0 to AN3).
Figure 2.15.1 shows the Key Input Switch Block Diagram, and Table2.15.1 lists the Voltage of AD Input Pin and AD value
When Pushing Ken Input Switch.
Expansion
connector
AVcc
AVcc
4.7kΩ
AN0
18.7kΩ
6.98kΩ
3.16kΩ
1.18kΩ
SW4
SW3
SW2
SW1
AN0
R7S72100 (U1)
P1_8 / AN0
AVcc
AN1
18.7kΩ
6.98kΩ
3.16kΩ
1.18kΩ
SW8
SW7
SW6
SW5
AVcc
4.7kΩ
AN1
P1_9 / AN1
AVcc
AN2
18.7kΩ
6.98kΩ
3.16kΩ
SW12
SW11
SW10
AVcc
4.7kΩ
AN2
P1_10 / AN2
1.18kΩ
AVcc
SW9
AN3
2.37kΩ
23.7kΩ
Center
D
4.7kΩ
C
9.31kΩ
B
AVcc
4.7kΩ
AN3
P1_11 / AN3
931Ω
Note: Letters in Red indicate
functions in use.
A
SW13
Figure 2.15.1
Table2.15.1
Key Input Switch Block Diagram
Voltage of AD Input Pin and AD value When Pushing Ken Input Switch
Switch
Pin voltage (V)
10-bit AD value
12-bit AD value
SW1, SW5, SW9
0.66
205
822
SW2, SW6, SW10
1.33
412
1647
SW3, SW7, SW11
1.97
612
2448
SW4, SW8, SW12
2.64
818
3273
SW13-A
0.55
169
677
SW13-B
2.19
680
2722
SW13-C
1.65
512
2048
SW13-D
2.75
855
3418
SW13-Center
1.11
343
1373
* Calculated when Avcc is 3.3V, and Avss is 0V. The difference of the resisgors and the voltage is not included.
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
2-34
R7S72100 CPU (GENMAI) Optional Board
2.16
RTK7721000B00000BR
2.
Functional Specification
Power Configuration
The RTK7721000B00000BR is operated with 12V, 5V, and 3.3V supplied from the RTK772100BC00000BR. Analog
3.3V for the video DAC and the audio DAC and 8V for the CD deck are generated on the RTK7721000B00000BR.
Figure 2.16.1 shows the Power Configuration Diagram.
System
power
supply
Vss
(DC12V)
12V external
power supply
(J23)
Vss
Expansion
connector
Power switch
(SW4)
DC power jack
(J25)
D12V
D8V
12V→8V
12V→5V
CD deck
D5V
IEBus transceiver, LIN transceiver,
SIM card slot, UART connector, HCI connector,
LCD panel connector, CMOS camera, DV connector
Power select
jumper
(JP14)
5V→3.3V
A3.3V
Key input switch
D3.3V
Bus switch, IrDA module, HCI connector,
CD deck connector, LCD panel connector,
Oscillator, DV connector, Clock buffer, Audio DAC
AN3V
Video DAC, Audio DAC
Figure 2.16.1
Power Configuration Diagram
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
2-35
R7S72100 CPU (GENMAI) Optional Board
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
RTK7721000B00000BR
2.
Functional Specification
2-36
Figure 3.1.1
Sep. 06, 2013
R20UT2696EJ0005 Rev.0.05
J15: Analog RGB connector
J3: UART connector
3.
CN5: Expansion connector
CN6: Expansion connector
RTK7721000B00000BR
J2: SIM card slot
CN4: Expansion connector
Connector Overview
J9: Lineout pin jack
3.1
J6: Lineout pin jack
Operational Specification
J8: CD deck connector
CN7: Expansion connector
CN8: Expansion connector
J5: LIN connector
3.
CN2: Expansion connector
CN9: Expansion connector
J4: IEBus connector
J14: LCD panel connector
(ch1, R0P7724LE0011RL)
J16: Analog RGB connector
R7S72100 CPU (GENMAI) Optional Board
Operational Specification
Figure 3.1.1 and Figure 3.1.2 show the RTK7721000B00000BR Connector Layouts
RTK7721000B00000BR Connector Layout (Top View of Component Side)
3-1
Figure 3.1.2
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
J18: Digital video input connector
(ch0)
J17: CMOS camera connector
(MT9V024IA7XTCD ES)
3.
J12: LCD panel connector
(ch1, LCD-KIT-B01)
RTK7721000B00000BR
J13: LCD panel connector
(ch1, general purpose)
J19: Digital video input connector
(ch1)
J7: HCI connector
J10: LCD panel connector
(ch0, LCD-KIT-B01)
J11: LCD panel connector
(ch0, general purpose)
R7S72100 CPU (GENMAI) Optional Board
Operational Specification
RTK7721000B00000BR Connector Layout (Top View of Solder Side)
3-2
R7S72100 CPU (GENMAI) Optional Board
3.1.1
RTK7721000B00000BR
3.
Operational Specification
Expansion Connectors (CN1 to CN9)
2
1
20
19
2
CN5: Expansion connector
2
30
2
33
1
29
1
2
1
20
19
29
1
20
2
19
1
CN4: Expansion connector
CN9: Expansion connector
2
CN2: Expansion connector
29
30
Pinout Diagram of Expansion Connector
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
34
1
30
Figure 3.1.3
CN6: Expansion connector
CN7: Expansion connector
CN8: Expansion connector
The RTK7721000B00000BR has expansion connectors (CN2, CN4 to CN9) to connect with the RTK772100BC00000BR.
Figure 3.1.3 shows the Pinout Diagram of Expansion Connector, and Table 3.1.1 to Table 3.1.7 list the Expansion
Connector Pin Assignments.
3-3
R7S72100 CPU (GENMAI) Optional Board
Table 3.1.1
RTK7721000B00000BR
3.
Operational Specification
Expansion Connector Pin Assignments 1 (CN2)
Pin No.
Signal Name
Pin No.
Signal Name
1
Vss
2
CKIO
3
Vss
4
Vss
5
P11_11 / DV0_DATA23 / SD_D2_0 / RxD5 /
6
P11_10 / DV0_DATA22 / SD_D3_0 / TxD5 /
MMC_D2 / LCD0_TCON3
MMC_D3 / LCD0_TCON4
7
P11_9 / DV0_DATA21 / SD_CMD_0 / SCK5 /
8
9
3VCC
10
3VCC
P11_7 / DV0_DATA19 / SD_D0_0 / CTS5 /
12
P11_6 / DV0_DATA18 / SD_D1_0 / SSIDATA4 /
MMC_CMD / LCD0_TCON5
11
MMC_CLK / LCD0_TCON6
MMC_D0 / LCD0_DATA0
13
P11_5 / DV0_DATA17 / SD_WP_0 / SSIWS4 /
MMC_D1 / LCD0_DATA1
14
LCD0_DATA2
15
17
16
P11_15 / SPDIF_OUT / MISO1 / IRQ1 /
18
23
P11_13 / CTx1 / SSL10 / LCD0_TCON4 /
20
22
P7_7 / WE1/DQMLU / DV0_DATA23 /
24
P7_5 / RD/WR / DV0_DATA21 / ET_TXD1 /
P7_3 / CAS / DV0_DATA19 / ET_TXEN /
26
P7_1 / CS3 / DV0_DATA17 / ET_TXCLK /
TXD4 / DV0_CLK / SSISCK1 / TIOC0B
: 5V system power supply,
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
: 3.3V system power supply,
P7_8 / RD / SSISCK3 / CRx0 / TIOC3A / IRQ1
P7_6 / WE0/DQMLL / DV0_DATA22 /
P7_4 / CKE / DV0_DATA20 / ET_TXD0 / TXD7 /
SSITxD1 / TIOC1A
28
SCK7 / CTx2 / SSIRxD1 / TIOC0D
29
P11_12 / CRx1 / RSPCK1 / IRQ3 / MMC_D4 /
ET_TXD2 / CTS7 / SSIWS2 / TIOC2A
RXD7 / SSISCK2 / TIOC1B
27
P11_14 / SPDIF_IN / MOSI1 / LCD0_TCON5 /
LCD0_TCON2
Vss
ET_TXD3 / RTS7 / SSIDATA2 / TIOC2B
25
3VCC
MMC_D6 / LCD0_TCON0
MMC_D5 / LCD0_TCON1
21
P11_4 / DV0_DATA16 / SD_CD_0 / SSISCK4 /
MMC_CD / LCD0_DATA3
3VCC
MMC_D7 / LCD0_CLK
19
P11_8 / DV0_DATA20 / SD_CLK_0 / RTS5 /
P7_2 / RAS / DV0_DATA18 / ET_TXER / RXD4 /
CRx2 / SSIWS1 / TIOC0C
30
P7_0 / MD_BOOT2 / CS0 / DV0_DATA16 /
ET_MDC / SCK4 / LTXD0 / TIOC0A
: GND
3-4
R7S72100 CPU (GENMAI) Optional Board
Table 3.1.2
RTK7721000B00000BR
3.
Operational Specification
Expansion Connector Pin Assignments 2 (CN4)
Pin No.
Signal Name
Pin No.
Signal Name
1
NMI
2
RES#
3
NC
4
NC
5
P3_1 / LCD0_TCON0 / ET_TXER / IRQ6 /
6
P3_0 / LCD0_CLK / ET_TXCLK / IRQ2 / SCK2 /
TxD2 / SCI_TXD1 / AUDIO_CLK / PWM2B /
SCI_SCK1 / TxD2 / PWM2A / RSPCK3
SSL30
7
P3_3 / LCD0_TCON2 / ET_MDIO / IRQ4 / BS /
8
P3_2 / LCD0_TCON1 / ET_TXEN / RxD2 /
SCI_CTS1 / RTS1 / DACK0 / PWM2D / MISO3
9
11
SCI_RXD1 / TEND0 / PWM2C / MOSI3
Vss
10
Vss
P3_5 / LCD0_TCON4 / ET_RXER / SSIWS1 /
12
P3_4 / LCD0_TCON3 / ET_RXCLK / SSISCK1 /
AUDIO_XOUT3 / SCI_TXD0 / TIOC3B / TxD3
13
AUDIO_XOUT2 / SCI_SCK0 / TIOC3A / SCK3
P3_7 / LCD0_TCON6 / SSITxD1 /
14
P3_6 / LCD0_TCON5 / ET_RXDV / SSIRxD1 /
LCD1_EXTCLK / SCI_CTS0/RTS0 / TIOC3D /
SCI_RXD0 / TIOC3C / RxD3
CS1 / WDTOVF
15
Vss
16
Vss
17
P10_3 / TCLKD / PWM2D / ET_CRS /
18
P10_2 / DV0_HSYNC / TCLKC / PWM2C /
LCD0_DATA20 / VIO_FLD
19
ET_TXEN / LCD0_DATA21 / VIO_HD
P10_1 / DV0_VSYNC / TCLKB / PWM2B /
20
P10_0 / DV0_CLK / TCLKA / PWM2A /
ET_TXER / LCD0_DATA22 / VIO_VD
: 5V system power supply,
Table 3.1.3
ET_TXCLK / LCD0_DATA23 / VIO_CLK
: 3.3V system power supply,
: GND
Expansion Connector Pin Assignments 3 (CN5)
Pin No.
Signal Name
Pin No.
Signal Name
1
+12V
2
+12V
3
+12V
4
+12V
5
+12V
6
+12V
7
P1_15 / AN7
8
P1_14 / AN6 / ET_COL
9
AVcc
10
AVcc
11
P1_13 / AN5 / DV0_HSYNC / WAIT
12
P1_12 / AN4 / DV0_VSYNC / VIO_FLD
13
AVss
14
AVss
15
P1_11 / AN3 / IRQ5 / TCLKD
16
P1_10 / AN2 / IRQ4 / TCLKB
17
VBUS
18
VBUS
19
P1_9 / AN1 / IRQ3 / VIO_D15 / DV0_DATA15
20
P1_8 / AN0 / IRQ2 / DREQ0 / VIO_D14 /
DV0_DATA14
: 5V system power supply,
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
: 3.3V system power supply,
: GND
3-5
R7S72100 CPU (GENMAI) Optional Board
Table 3.1.4
Signal Name
Pin No.
P3_9 / LCD0_DATA1 / NAF1 / TRACEDATA1 /
2
TIOC4B / SD_WP_1 / IRQ6
3
P3_11 / LCD0_DATA3 / NAF3 / TRACEDATA3 /
5
5VCC
Operational Specification
7
5VCC
9
P3_13 / LCD0_DATA5 / NAF5 / AUDIO_XOUT /
P3_8 / LCD0_DATA0 / NAF0 / TRACEDATA0 /
P3_10 / LCD0_DATA2 / NAF2 / TRACEDATA2 /
TIOC4C / SD_D1_1 / MMC_D1
6
5VCC
8
5VCC
10
SD_CMD_1 / MMC_CMD
P3_15 / LCD0_DATA7 / NAF7 / TRACECTRL /
Signal Name
TIOC4A / SD_CD_1 / MMC_CD
4
TIOC4D / SD_D0_1 / MMC_D0
11
3.
Expansion Connector Pin Assignments 4 (CN6)
Pin No.
1
RTK7721000B00000BR
P3_12 / LCD0_DATA4 / NAF4 / SD_CLK_1 /
MMC_CLK
12
SD_D2_1 / MMC_D2
P3_14 / LCD0_DATA6 / NAF6 / TRACECLK /
SD_D3_1 / MMC_D3
13
3VCC
14
3VCC
15
P4_1 / LCD0_DATA9 / TIOC0B / FCLE / SCK2 /
16
P4_0 / LCD0_DATA8 / TIOC0A / FRE /
SSL40 / MMC_D5
17
RSPCK4 / MMC_D4
P4_3 / LCD0_DATA11 / TIOC0D / FWE / CTx3 /
18
RxD2 / MISO4 / MMC_D7
P4_2 / LCD0_DATA10 / TIOC0C / FALE / CRx3 /
TxD2 / MOSI4 / MMC_D6
19
Vss
20
Vss
21
P10_5 / DV0_DATA1 / TIOC0B / PWM2F /
22
P10_4 / DV0_DATA0 / TIOC0A / PWM2E /
ET_TXD1 / LCD0_DATA18 / VIO_D1
23
P10_7 / DV0_DATA3 / TIOC0D / PWM2H /
ET_TXD0 / LCD0_DATA19 / VIO_D0
24
ET_TXD3 / LCD0_DATA16 / VIO_D3
25
27
ET_TXD2 / LCD0_DATA17 / VIO_D2
Vss
26
P4_5 / LCD0_DATA13 / SSL10 / TIOC4B /
28
PWM2F / SSIWS0 / DV0_DATA13
29
P4_7 / LCD0_DATA15 / MISO1 / TIOC4D /
PWM2H / SSITxD0 / DV0_DATA15
: 5V system power supply,
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
: 3.3V system power supply,
P10_6 / DV0_DATA2 / TIOC0C / PWM2G /
Vss
P4_4 / LCD0_DATA12 / RSPCK1 / TIOC4A /
PWM2E / SSISCK0 / DV0_DATA12
30
P4_6 / LCD0_DATA14 / MOSI1 / TIOC4C /
PWM2G / SSIRxD0 / DV0_DATA14
: GND
3-6
R7S72100 CPU (GENMAI) Optional Board
Table 3.1.5
RTK7721000B00000BR
3.
Operational Specification
Expansion Connector Pin Assignments 5 (CN7)
Pin No.
Signal Name
Pin No.
Signal Name
1
AUDIO_XTAL1
2
AUDIO_XTAL2
3
Vss
4
Vss
5
P10_9 / DV0_DATA5 / TIOC1B / ET_RXD1 /
6
P10_8 / DV0_DATA4 / TIOC1A / ET_RXD0 /
LCD0_DATA14 / VIO_D5
7
P10_11 / DV0_DATA7 / TIOC2B / ET_RXD3 /
LCD0_DATA15 / VIO_D4
8
LCD0_DATA12 / VIO_D7
9
P10_13 / DV0_DATA9 / SSIWS1 / SSL00 /
LCD0_DATA13 / VIO_D6
10
LCD0_DATA10 / VIO_D9
11
P10_15 / DV0_DATA11 / SSITxD1 / MISO0 /
P4_9 / LCD0_DATA17 / LCD1_TCON4 /
P10_12 / DV0_DATA8 / SSISCK1 / RSPCK0 /
LCD0_DATA11 / VIO_D8
12
LCD0_DATA8 / VIO_D11
13
P10_10 / DV0_DATA6 / TIOC2A / ET_RXD2 /
P10_14 / DV0_DATA10 / SSIRxD1 / MOSI0 /
LCD0_DATA9 / VIO_D10
14
SD_WP_0 / SSIWS5 / CRx2 / TxD0 / IRQ1
P4_8 / LCD0_DATA16 / LCD1_TCON3 /
SD_CD_0 / MMC_CD / SSISCK5 / CTx2 /
SCK0 / IRQ0
15
P4_11 / LCD0_DATA19 / LCD1_TCON6 /
16
P4_10 / LCD0_DATA18 / LCD1_TCON5 /
SD_D1_0 / MMC_D1 / SSIRxD5 / RxD0 / IRQ2
SD_D0_0 / MMC_D0 / SSITxD5 / CTx4 / SCK1 /
IRQ3
17
19
21
23
P4_13 / LCD0_DATA21 / LCD1_TCON0 /
18
SD_CLK_0 / MMC_CLK / SPBIO10_1 /
SSIWS3 / RxD1 / IRQ5
SSISCK3 / TxD1 / IRQ4
P4_15 / LCD0_DATA23 / LCD1_TCON2 /
20
SD_D3_0 / MMC_D3 / SPBIO21_1 / SSIRxD3 /
RxD2 / IRQ7
TxD2 / IRQ6
Vss
22
P2_1 / D17 / ET_TXER / DV0_DATA1 /
24
29
Vss
P2_0 / D16 / ET_TXCLK / DV0_DATA0 /
SPBIO00_1 / MLB_CLK / IRQ5 / VIO_D0 /
LCD0_DATA16
LCD0_DATA17
27
P4_14 / LCD0_DATA22 / LCD1_TCON1 /
SD_D2_0 / MMC_D2 / SPBIO31_1 / SSITxD3 /
SPBIO10_1 / MLB_DAT / TIOC2A / VIO_D1 /
25
P4_12 / LCD0_DATA20 / LCD1_CLK /
SD_CMD_0 / MMC_CMD / SPBIO11_1 /
P2_3 / D19 / ET_CRS / DV0_DATA3 /
26
P2_2 / D18 / ET_TXEN / DV0_DATA2 /
SPBIO30_1 / IERxD / CTS1 / VIO_D3 /
SPBIO20_1 / MLB_SIG / TIOC2B / VIO_D2 /
LCD0_DATA19
LCD0_DATA18
P2_5 / D21 / ET_TXD1 / DV0_DATA5 /
28
P2_4 / D20 / ET_TXD0 / DV0_DATA4 /
SSIWS5 / SPBSSL_1 / TxD1 / VIO_D5 /
SSISCK5 / SPBCLK_1 / SCK1 / VIO_D4 /
LCD0_DATA21
LCD0_DATA20
P2_7 / D23 / ET_TXD3 / DV0_DATA7 /
30
P2_6 / D22 / ET_TXD2 / DV0_DATA6 /
SSIRxD5 / RxD1 / VIO_D6 / LCD0_DATA22
SSITxD5 / IETxD / RTS1 / VIO_D7 /
LCD0_DATA23
31
33
P2_9 / D25 / ET_RXD1 / DV0_DATA9 /
32
P2_8 / D24 / ET_RXD0 / DV0_DATA8 /
SSIWS0 / LRXD0 / LCD1_DATA9 / VIO_D9 /
SSISCK0 / LCD0_TCON6 / LCD1_DATA8 /
SSL40
VIO_D8 / RSPCK4
P2_11 / D27 / ET_RXD3 / DV0_DATA11 /
34
P2_10 / D26 / ET_RXD2 / DV0_DATA10 /
SSITxD0 / TIOC1A / LCD1_DATA11 /
SSIRxD0 / LTXD0 / LCD1_DATA10 /
VIO_D11 / MISO4
VIO_D10 / MOSI4
: 5V system power supply,
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
: 3.3V system power supply,
: GND
3-7
R7S72100 CPU (GENMAI) Optional Board
Table 3.1.6
RTK7721000B00000BR
Signal Name
Pin No.
1
P3_4 / LCD0_TCON3 / ET_RXCLK / SSISCK1 /
2
AUDIO_XOUT2 / SCI_SCK0 / TIOC3A / SCK3
P3_6 / LCD0_TCON5 / ET_RXDV / SSIRxD1 /
5
3VCC
4
6
P2_13 / D29 / SSL00 / DV0_DATA13 /
8
SCI_RXD0 / TIOC3C / RxD3
10
P2_14 / D30 / MOSI0 / DV0_DATA14 /
SPBIO21_0 / CRx4 / TxD0 / LCD1_DATA14 /
LCD1_DATA15 / IRQ1
IRQ0
Vss
12
P1_1 / SDA0 / DV0_DATA17 / TCLKC / IRQ1 /
14
P1_3 / SDA1 / DV0_DATA19 / ET_COL / IRQ3 /
P1_7 / SDA3 / DV1_HSYNC / LRXD0 / IRQ7 /
VIO_D13 / DV0_DATA13
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
P1_0 / SCL0 / DV0_DATA16 / TCLKA / IRQ0 /
16
P1_2 / SCL1 / DV0_DATA18 / FRB / IRQ2 /
LCD1_EXTCLK
P1_5 / SDA2 / DV1_CLK / CRx4 / IRQ5 /
: 5V system power supply,
Vss
VIO_VD / DV0_VSYNC
18
VIO_CLK / LCD1_EXTCLK
19
P2_12 / D28 / RSPCK0 / DV0_DATA12 /
SPBIO31_0 / CAN_CLK / RxD0 /
ADTRG
17
3VCC
TIOC1B
P2_15 / D31 / MISO0 / DV0_DATA15 /
VIO_HD / DV0_HSYNC
15
P3_5 / LCD0_TCON4 / ET_RXER / SSIWS1 /
SPBIO01_0 / CRx3 / IRQ6 / LCD1_DATA12 /
IRQ7
13
P3_3 / LCD0_TCON2 / ET_MDIO / IRQ4 / BS /
AUDIO_XOUT3 / SCI_TXD0 / TIOC3B / TxD3
SPBIO11_0 / CTx3 / SCK0 / LCD1_DATA13 /
11
Signal Name
SCI_CTS1 / RTS1 / DACK0 / PWM2D / MISO3
3
9
Operational Specification
Expansion Connector Pin Assignments 6 (CN8)
Pin No.
7
3.
: 3.3V system power supply,
P1_4 / SCL2 / DV0_CLK / CRx1 / IRQ4 /
CAN_CLK
20
P1_6 / SCL3 / DV1_VSYNC / IERxD / IRQ6 /
VIO_D12 / DV0_DATA12
: GND
3-8
R7S72100 CPU (GENMAI) Optional Board
Table 3.1.7
3
Signal Name
Pin No.
P5_1 / TXCLKOUTM / LCD1_DATA1 /
2
RSPCK3
P5_3 / TXOUT2M / LCD1_DATA3 /
4
P5_2 / TXOUT2P / LCD1_DATA2 /
LCD0_DATA18 / DV1_DATA2 / SCK3 /
TIOC1B / MOSI3
P5_5 / TXOUT1M / LCD1_DATA5 /
6
P5_4 / TXOUT1P / LCD1_DATA4 /
LCD0_DATA21 / DV1_DATA5 / AUDIO_XOUT /
LCD0_DATA20 / DV1_DATA4 / RxD3 /
TIOC0C / FCE / DV0_DATA13
TIOC3D / DV0_DATA12
P5_7 / TXOUT0M / LCD1_DATA7 /
8
P5_6 / TXOUT0P / LCD1_DATA6 /
LCD0_DATA22 / DV1_DATA6 / TxD6 / IRQ6 /
SPDIF_IN / DV0_DATA14
TIOC0D / SPDIF_OUT / DV0_DATA15
11
P5_0 / TXCLKOUTP / LCD1_DATA0 /
LCD0_DATA16 / DV1_DATA0 / TxD4 / TIOC0A /
LCD0_DATA23 / DV1_DATA7 / RxD6 /
9
Signal Name
TIOC0B / SSL30
TIOC3C / MISO3
7
Operational Specification
LCD0_DATA17 / DV1_DATA1 / RxD4 /
LCD0_DATA19 / DV1_DATA3 / TxD3 /
5
3.
Expansion Connector Pin Assignments 7 (CN9)
Pin No.
1
RTK7721000B00000BR
Vss
10
Vss
P5_8 / LCD0_EXTCLK / IRQ0 / DV1_CLK /
12
Vss
Vss
14
Vss
P5_10 / WE3/DQMUU/AH / DV0_HSYNC /
16
DV0_CLK / CS2
13
15
CTx1 / IETxD / LCD1_DATA17
P5_9 / WE2/DQMUL / ET_MDC /
DV0_VSYNC / IRQ2 / CRx1 / IERxD /
LCD1_DATA16
17
Vss
18
19
P9_3 / LCD1_DATA19 / SPBSSL_0 / TxD1
20
Vss
P9_2 / LCD1_DATA18 / SPBCLK_0 / LTXD0 /
SCK1 / A0
21
P9_5 / LCD1_DATA21 / SPBIO10_0 /
22
P9_4 / LCD1_DATA20 / SPBIO00_0 / RxD1
24
P9_6 / LCD1_DATA22 / SPBIO20_0 / SSIWS2 /
SSISCK2 / CTS1 / CS4
23
P9_7 / LCD1_DATA23 / SPBIO30_0 /
SSIDATA2 / TIOC1A
25
27
RTS1 / CS5
3VCC
26
P11_1 / DV0_DATA13 / TIOC4B / TxD6 /
28
LCD0_DATA6 / VIO_D13
29
P11_3 / DV0_DATA15 / TIOC4D /
LCD0_DATA4 / VIO_D15
: 5V system power supply,
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
: 3.3V system power supply,
3VCC
P11_0 / DV0_DATA12 / TIOC4A / SCK6 /
LCD0_DATA7 / VIO_D12
30
P11_2 / DV0_DATA14 / TIOC4C / RxD6 /
LCD0_DATA5 / VIO_D14
: GND
3-9
R7S72100 CPU (GENMAI) Optional Board
3.1.2
RTK7721000B00000BR
3.
Operational Specification
SIM Card Slot (J2)
The RTK7721000B00000BR has a SIM card slot (J2).
Figure 3.1.4 shows the Pinout Diagram of SIM Card Slot, and Table 3.1.8 lists the SIM Card Slot Pin Assignments.
Top view of
component side
1
5
2
6
3
7
Figure 3.1.4
Table 3.1.8
J2
Pinout Diagram of SIM Card Slot
SIM Card Slot Pin Assignments
Pin No.
Signal Name
1
+5V
2
RST (P3_3 / LCD0_TCON2 / ET_MDIO / IRQ4 / BS / SCI_CTS1 / RTS1 / DACK0 / PWM2D / MISO3)
3
CLK (P3_4 / LCD0_TCON3 / ET_RXCLK / SSISCK1 / AUDIO_XOUT2 / SCI_SCK0 / TIOC3A / SCK3)
4
NC (without pins)
5
GND (Vss)
6
+3.3V
7
I/O (P3_5 / LCD0_TCON4 / ET_RXER / SSIWS1 / AUDIO_XOUT3 / SCI_TXD0 / TIOC3B / TxD3, and
P3_6 / LCD0_TCON5 / ET_RXDV / SSIRxD1 / SCI_RXD0 / TIOC3C / RxD3)
8
NC (without pins)
Note: Bold letters indicate setting functions
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
3-10
R7S72100 CPU (GENMAI) Optional Board
3.1.3
RTK7721000B00000BR
3.
Operational Specification
UART Connector (J3)
The RTK7721000B00000BR has a UART connector (J3).
Figure 3.1.5 shows the Pinout Diagram of UART Connector, and Table 3.1.9 lists the UART Connector Pin Assignments.
Top view of
component side
5
4
3
2
1
Figure 3.1.5
Table 3.1.9
J3
Pinout Diagram of UART Connector
UART Connector Pin Assignments
Pin No.
Signal Name
1
+5V
2
SCK (P3_4 / LCD0_TCON3 / ET_RXCLK / SSISCK1 / AUDIO_XOUT2 / SCI_SCK0 / TIOC3A / SCK3)
3
TXD (P3_5 / LCD0_TCON4 / ET_RXER / SSIWS1 / AUDIO_XOUT3 / SCI_TXD0 / TIOC3B / TxD3)
4
RXD (P3_6 / LCD0_TCON5 / ET_RXDV / SSIRxD1 / SCI_RXD0 / TIOC3C / RxD3)
5
GND (Vss)
Note: Bold letters indicate setting functions
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
3-11
R7S72100 CPU (GENMAI) Optional Board
3.1.4
RTK7721000B00000BR
3.
Operational Specification
IEBus Connector (J4)
The RTK7721000B00000BR has an IEBus connector (J4).
Figure 3.1.6 shows the Pinout Diagram of IEBus Connector, and Table 3.1.10 lists the IEBus Connector Pin Assignments.
Top view of
component side
1 2 3 4
J4
Figure 3.1.6
Pinout Diagram of IEBus Connector
Table 3.1.10
IEBus Connector Pin Assignments
Pin No.
Signal Name
1
+5V
2
BUS+
3
BUS-
4
GND (Vss)
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
3-12
R7S72100 CPU (GENMAI) Optional Board
3.1.5
RTK7721000B00000BR
3.
Operational Specification
LIN Connector (J5)
The RTK7721000B00000BR has a LIN connector (J5).
Figure 3.1.7 shows the Pinout Diagram of LIN Connector, and Table 3.1.11 lists the LIN Connector Pin Assignments.
Top view of
component side
J5
1 2 3
Figure 3.1.7
Pinout Diagram of LIN Connector
Table 3.1.11
LIN Connector Pin Assignments
Pin No.
Signal Name
1
+5V
2
LIN
3
GND (Vss)
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
3-13
R7S72100 CPU (GENMAI) Optional Board
3.1.6
RTK7721000B00000BR
3.
Operational Specification
Lineout Pin Jacks (J6 and J9)
The RTK7721000B00000BR has two lineout pin jacks (J6 and J9).
Figure 3.1.8 shows the Pinout Diagram of Lineout Pin Jacks, and Table 3.1.12 lists the Lineout Pin Jack Pin Assignments.
Top view of
component side
J9
J6
1
2
Figure 3.1.8
Pinout Diagram of Lineout Pin Jacks
Table 3.1.12
Lineout Pin Jack Pin Assignments
Pin No.
1
3
4
3
2
4
Signal Name
J6
J9
1
GND (AVss)
2
AOUTL (Lch analog output pin of audio DAC 1)
AOUTL (Lch analog output pin of audio DAC 2)
3
AOUTR (Rch analog output pin of audio DAC 1)
AOUTR (Rch analog output pin of audio DAC 2)
4
NC
NC
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
GND (AVss)
3-14
R7S72100 CPU (GENMAI) Optional Board
3.1.7
RTK7721000B00000BR
3.
Operational Specification
HCI Connector (J7)
The RTK7721000B00000BR has an HCI connector (J7).
Figure 3.1.9 shows the Pinout Diagram of HCI Connector, and Table 3.1.13 lists the HCI Connector Pin Assignments.
Top view of
solder side
2
J7
1
20
19
Figure 3.1.9
Pinout Diagram of HCI Connector
Table 3.1.13
HCI Connector Pin Assignments
Pin No.
Signal Name
Pin No.
Signal Name
1
AUDIO_XOUT
2
GND (Vss)
3
GND (Vss)
4
P3_1 / LCD0_TCON0 / ET_TXER / IRQ6 /
TxD2 / SCI_TXD1 / AUDIO_CLK / PWM2B /
SSL30
5
P1_0 / SCL0 / DV0_DATA16 / TCLKA / IRQ0 /
6
+3.3V
8
P7_8 / RD / SSISCK3 / CRx0 / TIOC3A / IRQ1
VIO_VD / DV0_VSYNC
7
P1_1 / SDA0 / DV0_DATA17 / TCLKC / IRQ1 /
VIO_HD / DV0_HSYNC
9
+3.3V
10
P2_4 / D20 / ET_TXD0 / DV0_DATA4 /
SSISCK5 / SPBCLK_1 / SCK1 / VIO_D4 /
LCD0_DATA20
11
P2_5 / D21 / ET_TXD1 / DV0_DATA5 /
12
P2_6 / D22 / ET_TXD2 / DV0_DATA6 /
SSIRxD5 / RxD1 / VIO_D6 / LCD0_DATA22
SSIWS5 / SPBSSL_1 / TxD1 / VIO_D5 /
LCD0_DATA21
13
P2_7 / D23 / ET_TXD3 / DV0_DATA7 /
14
+5V
SSITxD5 / IETxD / RTS1 / VIO_D7 /
LCD0_DATA23
15
+5V
16
P7_6 / WE0/DQMLL / DV0_DATA22 /
ET_TXD2 / CTS7 / SSIWS2 / TIOC2A
17
P7_7 / WE1/DQMLU / DV0_DATA23 /
18
ET_TXD3 / RTS7 / SSIDATA2 / TIOC2B
19
P7_4 / CKE / DV0_DATA20 / ET_TXD0 / TXD7 /
P7_5 / RD/WR / DV0_DATA21 / ET_TXD1 /
RXD7 / SSISCK2 / TIOC1B
20
GND (Vss)
SSITxD1 / TIOC1A
Note: Bold letters indicate setting functions
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
3-15
R7S72100 CPU (GENMAI) Optional Board
3.1.8
RTK7721000B00000BR
3.
Operational Specification
CD Deck Connector (J8)
The RTK7721000B00000BR has a CD deck connector (J8).
Figure 3.1.10 shows the Pinout Diagram of CD Deck Connector, and Table 3.1.14 lists the CD Deck Connector Pin
Assignments.
Top view of
component side
1
22
J8
Figure 3.1.10
Table 3.1.14
Pinout Diagram of CD Deck Connector
CD Deck Connector Pin Assignments
Pin No.
Signal Name
Pin No.
Signal Name
1
GND (Vss)
2
GND (Vss)
3
+8V
4
+8V
5
FLAG6 (P1_13 / AN5 / DV0_HSYNC / WAIT)
6
NC
7
CDRST (RES#)
8
GND (Vss)
9
+3.3V
10
+3.3V
11
GND (Vss)
12
CDFS (P3_3 / LCD0_TCON2 / ET_MDIO /
IRQ4 / BS / SCI_CTS1 / RTS1 / DACK0 /
PWM2D / MISO3)
13
15
CDSI (P4_2 / LCD0_DATA10 / TIOC0C /
FALE / CRx3 / TxD2 / MOSI4 / MMC_D6)
14
CDSO (P4_3 / LCD0_DATA11 / TIOC0D /
16
NC
18
IIS_LRCK (P3_5 / LCD0_TCON4 / ET_RXER /
CDCK (P4_0 / LCD0_DATA8 / TIOC0A / FRE /
RSPCK4 / MMC_D4)
FWE / CTx3 / RxD2 / MISO4 / MMC_D7)
17
IIS_BCK (P3_4 / LCD0_TCON3 / ET_RXCLK /
SSIWS1 / AUDIO_XOUT3 / SCI_TXD0 /
SSISCK1 / AUDIO_XOUT2 / SCI_SCK0 /
TIOC3B / TxD3)
TIOC3A / SCK3)
19
IIS_DATA (P3_6 / LCD0_TCON5 / ET_RXDV /
20
BLKCK (P3_1 / LCD0_TCON0 / ET_TXER /
IRQ6 / TxD2 / SCI_TXD1 / AUDIO_CLK /
SSIRxD1 / SCI_RXD0 / TIOC3C / RxD3)
PWM2B / SSL30)
21
TRANS
(P1_12 / AN4 / DV0_VSYNC / VIO_FLD)
22
NC
Note: Bold letters indicate setting functions
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
3-16
R7S72100 CPU (GENMAI) Optional Board
3.1.9
RTK7721000B00000BR
3.
Operational Specification
LCD Panel Connectors (J10 to J14)
40
Figure 3.1.11
40
1
39
2
2
40
1
39
39
40
39
2
1
1
Pinout Diagram of LCD Panel Connectors 1 (J10 to J13)
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
2
J12: LCD panel connector
(ch1, LCD-KIT-B01)
J13: LCD panel connector
(ch1, general purpose)
J10: LCD panel connector
(ch0, LCD-KIT-B01)
J11: LCD panel connector
(ch0, general purpose)
The RTK7721000B00000BR has five connectors (J10 to J14) with three types to connect the LCD panel.
Figure 3.1.11 and Figure 3.1.12 show the Pinout Diagram of LCD Panel Connectors. Table 3.1.15 to Table 3.1.20 list the
LCD panel connector Pin Assignments.
3-17
R7S72100 CPU (GENMAI) Optional Board
Table 3.1.15
RTK7721000B00000BR
3.
Operational Specification
LCD Panel Connector Pin Assignments 1 (J10: ch0, For LCD-KIT-B01)
Pin No.
Signal Name
Pin No.
2
Signal Name
1
+3.3V
+3.3V
3
+3.3V
4
GND (Vss)
5
GND (Vss)
6
B0 (P11_7 / DV0_DATA19 / SD_D0_0 / CTS5 /
7
B1 (P11_6 / DV0_DATA18 / SD_D1_0 /
8
MMC_D0 / LCD0_DATA0)
SSIDATA4 / MMC_D1 / LCD0_DATA1)
9
B3 (P11_4 / DV0_DATA16 / SD_CD_0 /
SSIWS4 / LCD0_DATA2)
10
SSISCK4 / MMC_CD / LCD0_DATA3)
11
B5 (P11_2 / DV0_DATA14 / TIOC4C / RxD6 /
B2 (P11_5 / DV0_DATA17 / SD_WP_0 /
B4 (P11_3 / DV0_DATA15 / TIOC4D /
LCD0_DATA4 / VIO_D15)
12
GND (Vss)
LCD0_DATA5 / VIO_D14)
13
G0 (P11_1 / DV0_DATA13 / TIOC4B / TxD6 /
14
LCD0_DATA6 / VIO_D13)
15
G2 (P10_15 / DV0_DATA11 / SSITxD1 /
16
MISO0 / LCD0_DATA8 / VIO_D11)
17
G4 (P10_13 / DV0_DATA9 / SSIWS1 / SSL00 /
R0 (P10_11 / DV0_DATA7 / TIOC2B /
18
R2(P10_9 / DV0_DATA5 / TIOC1B / ET_RXD1 /
20
R4 (P10_7 / DV0_DATA3 / TIOC0D / PWM2H /
R1 (P10_10 / DV0_DATA6 / TIOC2A /
ET_RXD2 / LCD0_DATA13 / VIO_D6)
22
LCD0_DATA14 / VIO_D5)
23
G5 (P10_12 / DV0_DATA8 / SSISCK1 /
RSPCK0 / LCD0_DATA11 / VIO_D8)
ET_RXD3 / LCD0_DATA12 / VIO_D7)
21
G3 (P10_14 / DV0_DATA10 / SSIRxD1 /
MOSI0 / LCD0_DATA9 / VIO_D10)
LCD0_DATA10 / VIO_D9)
19
G1 (P11_0 / DV0_DATA12 / TIOC4A / SCK6 /
LCD0_DATA7 / VIO_D12)
R3 (P10_8 / DV0_DATA4 / TIOC1A / ET_RXD0 /
LCD0_DATA15 / VIO_D4)
24
ET_TXD3 / LCD0_DATA16 / VIO_D3)
R5 (P10_6 / DV0_DATA2 / TIOC0C / PWM2G /
ET_TXD2 / LCD0_DATA17 / VIO_D2)
25
GND (Vss)
26
27
HSYNC (P11_11 / DV0_DATA23 / SD_D2_0 /
28
DE (P11_12 / CRx1 / RSPCK1 / IRQ3 /
MMC_D4 / LCD0_TCON2)
RxD5 / MMC_D2 / LCD0_TCON3)
29
GND (Vss)
VSYNC (P11_10 / DV0_DATA22 / SD_D3_0 /
TxD5 / MMC_D3 / LCD0_TCON4)
30
LCDCLK (P11_15 / SPDIF_OUT / MISO1 /
IRQ1 / MMC_D7 / LCD0_CLK)
31
GND (Vss)
32
+5V
33
+5V
34
+5V
35
NC
36
SDA (P1_1 / SDA0 / DV0_DATA17 / TCLKC /
IRQ1 / VIO_HD / DV0_HSYNC)
37
SCL (P1_0 / SCL0 / DV0_DATA16 / TCLKA /
38
IRQ0 / VIO_VD / DV0_VSYNC)
39
NC
INT (P11_13 / CTx1 / SSL10 / LCD0_TCON4 /
MMC_D5 / LCD0_TCON1)
40
RESET (P11_14 / SPDIF_IN / MOSI1 /
LCD0_TCON5 / MMC_D6 / LCD0_TCON0)
Note: Bold letters indicate setting functions
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
3-18
R7S72100 CPU (GENMAI) Optional Board
Table 3.1.16
Signal Name
Operational Specification
P11_7 / DV0_DATA19 / SD_D0_0 / CTS5 /
Pin No.
Signal Name
2
P11_6 / DV0_DATA18 / SD_D1_0 / SSIDATA4 /
MMC_D0 / LCD0_DATA0
3
3.
LCD Panel Connector Pin Assignments 2 (J11: ch0, for general purpose)
Pin No.
1
RTK7721000B00000BR
P11_5 / DV0_DATA17 / SD_WP_0 / SSIWS4 /
MMC_D1 / LCD0_DATA1
4
P11_4 / DV0_DATA16 / SD_CD_0 / SSISCK4 /
P11_3 / DV0_DATA15 / TIOC4D / LCD0_DATA4
MMC_CD / LCD0_DATA3
LCD0_DATA2
5
GND (Vss)
6
7
P11_2 / DV0_DATA14 / TIOC4C / RxD6 /
8
/ VIO_D15
LCD0_DATA5 / VIO_D14
9
P11_0 / DV0_DATA12 / TIOC4A / SCK6 /
P11_1 / DV0_DATA13 / TIOC4B / TxD6 /
LCD0_DATA6 / VIO_D13
10
GND (Vss)
LCD0_DATA7 / VIO_D12
11
P10_15 / DV0_DATA11 / SSITxD1 / MISO0 /
12
LCD0_DATA8 / VIO_D11
13
P10_13 / DV0_DATA9 / SSIWS1 / SSL00 /
14
LCD0_DATA10 / VIO_D9
15
GND (Vss)
P10_14 / DV0_DATA10 / SSIRxD1 / MOSI0 /
LCD0_DATA9 / VIO_D10
P10_12 / DV0_DATA8 / SSISCK1 / RSPCK0 /
LCD0_DATA11 / VIO_D8
16
P10_11 / DV0_DATA7 / TIOC2B / ET_RXD3 /
LCD0_DATA12 / VIO_D7
17
P10_10 / DV0_DATA6 / TIOC2A / ET_RXD2 /
18
LCD0_DATA13 / VIO_D6
19
P10_8 / DV0_DATA4 / TIOC1A / ET_RXD0 /
P10_9 / DV0_DATA5 / TIOC1B / ET_RXD1 /
LCD0_DATA14 / VIO_D5
20
GND (Vss)
22
P10_6 / DV0_DATA2 / TIOC0C / PWM2G /
LCD0_DATA15 / VIO_D4
21
P10_7 / DV0_DATA3 / TIOC0D / PWM2H /
ET_TXD3 / LCD0_DATA16 / VIO_D3
23
P10_5 / DV0_DATA1 / TIOC0B / PWM2F /
ET_TXD2 / LCD0_DATA17 / VIO_D2
24
ET_TXD1 / LCD0_DATA18 / VIO_D1
P10_4 / DV0_DATA0 / TIOC0A / PWM2E /
ET_TXD0 / LCD0_DATA19 / VIO_D0
25
+3.3V
26
27
P10_2 / DV0_HSYNC / TCLKC / PWM2C /
28
P10_3 / TCLKD / PWM2D / ET_CRS /
LCD0_DATA20 / VIO_FLD
ET_TXEN / LCD0_DATA21 / VIO_HD
29
P10_0 / DV0_CLK / TCLKA / PWM2A /
P10_1 / DV0_VSYNC / TCLKB / PWM2B /
ET_TXER / LCD0_DATA22 / VIO_VD
30
+3.3V
ET_TXCLK / LCD0_DATA23 / VIO_CLK
31
P11_14 / SPDIF_IN / MOSI1 / LCD0_TCON5 /
32
MMC_D6 / LCD0_TCON0
33
P11_12 / CRx1 / RSPCK1 / IRQ3 / MMC_D4 /
34
LCD0_TCON2
35
+5V
P11_13 / CTx1 / SSL10 / LCD0_TCON4 /
MMC_D5 / LCD0_TCON1
P11_11 / DV0_DATA23 / SD_D2_0 / RxD5 /
MMC_D2 / LCD0_TCON3
36
P11_10 / DV0_DATA22 / SD_D3_0 / TxD5 /
MMC_D3 / LCD0_TCON4
37
P11_9 / DV0_DATA21 / SD_CMD_0 / SCK5 /
38
MMC_CMD / LCD0_TCON5
39
P11_15 / SPDIF_OUT / MISO1 / IRQ1 /
P11_8 / DV0_DATA20 / SD_CLK_0 / RTS5 /
MMC_CLK / LCD0_TCON6
40
+5V
MMC_D7 / LCD0_CLK
Note: Bold letters indicate setting functions
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
3-19
R7S72100 CPU (GENMAI) Optional Board
Table 3.1.17
RTK7721000B00000BR
3.
Operational Specification
LCD Panel Connector Pin Assignments 3 (J12: ch1, For LCD-KIT-B01)
Pin No.
Signal Name
Pin No.
2
Signal Name
1
+3.3V
3
+3.3V
4
GND (Vss)
5
GND (Vss)
6
B0 (P5_0 / TXCLKOUTP / LCD1_DATA0 /
LCD0_DATA16 / DV1_DATA0 / TxD4 / TIOC0A /
RSPCK3)
7
B1 (P5_1 / TXCLKOUTM / LCD1_DATA1 /
LCD0_DATA17 / DV1_DATA1 / RxD4 /
TIOC0B / SSL30)
8
B2 (P5_2 / TXOUT2P / LCD1_DATA2 /
LCD0_DATA18 / DV1_DATA2 / SCK3 /
TIOC1B / MOSI3)
9
B3 (P5_3 / TXOUT2M / LCD1_DATA3 /
LCD0_DATA19 / DV1_DATA3 / TxD3 /
TIOC3C / MISO3)
10
B4 (P5_4 / TXOUT1P / LCD1_DATA4 /
LCD0_DATA20 / DV1_DATA4 / RxD3 /
TIOC3D / DV0_DATA12)
11
B5 (P5_5 / TXOUT1M / LCD1_DATA5 /
LCD0_DATA21 / DV1_DATA5 / AUDIO_XOUT /
TIOC0C / FCE / DV0_DATA13)
12
GND (Vss)
13
G0 (P5_6 / TXOUT0P / LCD1_DATA6 /
LCD0_DATA22 / DV1_DATA6 / TxD6 / IRQ6 /
SPDIF_IN / DV0_DATA14)
14
G1 (P5_7 / TXOUT0M / LCD1_DATA7 /
LCD0_DATA23 / DV1_DATA7 / RxD6 /
TIOC0D / SPDIF_OUT / DV0_DATA15)
15
G2 (P2_8 / D24 / ET_RXD0 / DV0_DATA8 /
SSISCK0 / LCD0_TCON6 / LCD1_DATA8 /
VIO_D8 / RSPCK4)
16
G3 (P2_9 / D25 / ET_RXD1 / DV0_DATA9 /
SSIWS0 / LRXD0 / LCD1_DATA9 / VIO_D9 /
SSL40)
17
G4 (P2_10 / D26 / ET_RXD2 / DV0_DATA10 /
SSIRxD0 / LTXD0 / LCD1_DATA10 /
VIO_D10 / MOSI4)
18
G5 (P2_11 / D27 / ET_RXD3 / DV0_DATA11 /
SSITxD0 / TIOC1A / LCD1_DATA11 /
VIO_D11 / MISO4)
19
R0 (P2_12 / D28 / RSPCK0 / DV0_DATA12 /
SPBIO01_0 / CRx3 / IRQ6 / LCD1_DATA12 /
TIOC1B)
20
R1 (P2_13 / D29 / SSL00 / DV0_DATA13 /
SPBIO11_0 / CTx3 / SCK0 / LCD1_DATA13 /
IRQ7)
21
R2 (P2_14 / D30 / MOSI0 / DV0_DATA14 /
SPBIO21_0 / CRx4 / TxD0 / LCD1_DATA14 /
IRQ0)
22
R3 (P2_15 / D31 / MISO0 / DV0_DATA15 /
SPBIO31_0 / CAN_CLK / RxD0 /
LCD1_DATA15 / IRQ1)
23
R4 (P5_9 / WE2/DQMUL / ET_MDC /
DV0_VSYNC / IRQ2 / CRx1 / IERxD /
LCD1_DATA16)
24
R5 (P5_10 / WE3/DQMUU/AH / DV0_HSYNC /
CTx1 / IETxD / LCD1_DATA17)
25
GND (Vss)
26
DE (P4_14 / LCD0_DATA22 / LCD1_TCON1 /
SD_D3_0 / MMC_D3 / SPBIO21_1 / SSIRxD3 /
TxD2 / IRQ6)
27
HSYNC (P4_13 / LCD0_DATA21 /
LCD1_TCON0 / SD_CMD_0 / MMC_CMD /
SPBIO11_1 / SSIWS3 / RxD1 / IRQ5)
28
VSYNC (P4_15 / LCD0_DATA23 /
LCD1_TCON2 / SD_D2_0 / MMC_D2 /
SPBIO31_1 / SSITxD3 / RxD2 / IRQ7)
29
GND (Vss)
30
LCDCLK (P4_12 / LCD0_DATA20 / LCD1_CLK /
SD_CLK_0 / MMC_CLK / SPBIO10_1 /
SSISCK3 / TxD1 / IRQ4)
31
GND (Vss)
32
+5V
33
+5V
34
+5V
35
NC
36
SDA (P1_7 / SDA3 / DV1_HSYNC / LRXD0 /
IRQ7 / VIO_D13 / DV0_DATA13)
37
SCL (P1_6 / SCL3 / DV1_VSYNC / IERxD /
38
INT (P4_8 / LCD0_DATA16 / LCD1_TCON3 /
SD_CD_0 / MMC_CD / SSISCK5 / CTx2 /
SCK0 / IRQ0)
40
RESET (P4_9 / LCD0_DATA17 /
LCD1_TCON4 / SD_WP_0 / SSIWS5 / CRx2 /
TxD0 / IRQ1)
IRQ6 / VIO_D12 / DV0_DATA12)
39
NC
+3.3V
Note: Bold letters indicate setting functions
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
3-20
R7S72100 CPU (GENMAI) Optional Board
Table 3.1.18
RTK7721000B00000BR
3.
Operational Specification
LCD Panel Connector Pin Assignments 4 (J13: ch1, for general purpose)
Pin No.
Signal Name
Pin No.
Signal Name
1
P5_0 / TXCLKOUTP / LCD1_DATA0 /
LCD0_DATA16 / DV1_DATA0 / TxD4 /
TIOC0A / RSPCK3
2
P5_1 / TXCLKOUTM / LCD1_DATA1 /
LCD0_DATA17 / DV1_DATA1 / RxD4 / TIOC0B /
SSL30
3
P5_2 / TXOUT2P / LCD1_DATA2 /
LCD0_DATA18 / DV1_DATA2 / SCK3 /
TIOC1B / MOSI3
4
P5_3 / TXOUT2M / LCD1_DATA3 /
LCD0_DATA19 / DV1_DATA3 / TxD3 /
TIOC3C / MISO3
5
GND (Vss)
6
P5_4 / TXOUT1P / LCD1_DATA4 /
LCD0_DATA20 / DV1_DATA4 / RxD3 /
TIOC3D / DV0_DATA12
7
P5_5 / TXOUT1M / LCD1_DATA5 /
LCD0_DATA21 / DV1_DATA5 / AUDIO_XOUT /
TIOC0C / FCE / DV0_DATA13
8
P5_6 / TXOUT0P / LCD1_DATA6 /
LCD0_DATA22 / DV1_DATA6 / TxD6 / IRQ6 /
SPDIF_IN / DV0_DATA14
9
P5_7 / TXOUT0M / LCD1_DATA7 /
LCD0_DATA23 / DV1_DATA7 / RxD6 /
TIOC0D / SPDIF_OUT / DV0_DATA15
10
GND (Vss)
11
P2_8 / D24 / ET_RXD0 / DV0_DATA8 /
SSISCK0 / LCD0_TCON6 / LCD1_DATA8 /
VIO_D8 / RSPCK4
12
P2_9 / D25 / ET_RXD1 / DV0_DATA9 /
SSIWS0 / LRXD0 / LCD1_DATA9 / VIO_D9 /
SSL40
13
P2_10 / D26 / ET_RXD2 / DV0_DATA10 /
SSIRxD0 / LTXD0 / LCD1_DATA10 /
VIO_D10 / MOSI4
14
P2_11 / D27 / ET_RXD3 / DV0_DATA11 /
SSITxD0 / TIOC1A / LCD1_DATA11 /
VIO_D11 / MISO4
15
GND (Vss)
16
P2_12 / D28 / RSPCK0 / DV0_DATA12 /
SPBIO01_0 / CRx3 / IRQ6 / LCD1_DATA12 /
TIOC1B
17
P2_13 / D29 / SSL00 / DV0_DATA13 /
SPBIO11_0 / CTx3 / SCK0 / LCD1_DATA13 /
IRQ7
18
P2_14 / D30 / MOSI0 / DV0_DATA14 /
SPBIO21_0 / CRx4 / TxD0 / LCD1_DATA14 /
IRQ0
19
P2_15 / D31 / MISO0 / DV0_DATA15 /
SPBIO31_0 / CAN_CLK / RxD0 /
LCD1_DATA15 / IRQ1
20
GND (Vss)
21
P5_9 / WE2/DQMUL / ET_MDC / DV0_VSYNC /
IRQ2 / CRx1 / IERxD / LCD1_DATA16
22
P5_10 / WE3/DQMUU/AH / DV0_HSYNC /
CTx1 / IETxD / LCD1_DATA17
23
P9_2 / LCD1_DATA18 / SPBCLK_0 / LTXD0 /
SCK1 / A0
24
P9_3 / LCD1_DATA19 / SPBSSL_0 / TxD1
25
+3.3V
26
P9_4 / LCD1_DATA20 / SPBIO00_0 / RxD1
27
P9_5 / LCD1_DATA21 / SPBIO10_0 /
28
SSISCK2 / CTS1 / CS4
29
P9_7 / LCD1_DATA23 / SPBIO30_0 /
P9_6 / LCD1_DATA22 / SPBIO20_0 / SSIWS2 /
RTS1 / CS5
30
+3.3V
SSIDATA2 / TIOC1A
31
P4_13 / LCD0_DATA21 / LCD1_TCON0 /
SD_CMD_0 / MMC_CMD / SPBIO11_1 /
SSIWS3 / RxD1 / IRQ5
32
P4_14 / LCD0_DATA22 / LCD1_TCON1 /
SD_D3_0 / MMC_D3 / SPBIO21_1 / SSIRxD3 /
TxD2 / IRQ6
33
P4_15 / LCD0_DATA23 / LCD1_TCON2 /
SD_D2_0 / MMC_D2 / SPBIO31_1 / SSITxD3 /
RxD2 / IRQ7
34
P4_8 / LCD0_DATA16 / LCD1_TCON3 /
SD_CD_0 / MMC_CD / SSISCK5 / CTx2 /
SCK0 / IRQ0
35
+5V
36
P4_9 / LCD0_DATA17 / LCD1_TCON4 /
SD_WP_0 / SSIWS5 / CRx2 / TxD0 / IRQ1
37
P4_10 / LCD0_DATA18 / LCD1_TCON5 /
SD_D1_0 / MMC_D1 / SSIRxD5 / RxD0 / IRQ2
38
P4_11 / LCD0_DATA19 / LCD1_TCON6 /
SD_D0_0 / MMC_D0 / SSITxD5 / CTx4 / SCK1 /
IRQ3
39
P4_12 / LCD0_DATA20 / LCD1_CLK /
SD_CLK_0 / MMC_CLK / SPBIO10_1 /
SSISCK3 / TxD1 / IRQ4
40
+5V
Note: Bold letters indicate setting functions
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
3-21
R7S72100 CPU (GENMAI) Optional Board
RTK7721000B00000BR
3.
Operational Specification
Top view of
component side
59
60
J14
1
Figure 3.1.12
Table 3.1.19
2
Pinout Diagram of LCD Panel Connector 2 (J14)
LCD Panel Connector Pin Assignments 5-1 (J14: ch1, For R0P7724LE0011RL)
Pin No.
Signal Name
Pin No.
Signal Name
1
GND (Vss)
2
GND (Vss)
3
LCD0 (P5_0 / TXCLKOUTP / LCD1_DATA0 /
LCD0_DATA16 / DV1_DATA0 / TxD4 /
TIOC0A / RSPCK3)
4
LCD1 (P5_1 / TXCLKOUTM / LCD1_DATA1 /
LCD0_DATA17 / DV1_DATA1 / RxD4 /
TIOC0B / SSL30)
5
LCD2 (P5_2 / TXOUT2P / LCD1_DATA2 /
LCD0_DATA18 / DV1_DATA2 / SCK3 /
TIOC1B / MOSI3)
6
LCD3 (P5_3 / TXOUT2M / LCD1_DATA3 /
LCD0_DATA19 / DV1_DATA3 / TxD3 /
TIOC3C / MISO3)
7
LCD4 (P5_4 / TXOUT1P / LCD1_DATA4 /
LCD0_DATA20 / DV1_DATA4 / RxD3 /
TIOC3D / DV0_DATA12)
8
LCD5 (P5_5 / TXOUT1M / LCD1_DATA5 /
LCD0_DATA21 / DV1_DATA5 / AUDIO_XOUT /
TIOC0C / FCE / DV0_DATA13)
9
LCD6 (P5_6 / TXOUT0P / LCD1_DATA6 /
LCD0_DATA22 / DV1_DATA6 / TxD6 / IRQ6 /
SPDIF_IN / DV0_DATA14)
10
LCD7 (P5_7 / TXOUT0M / LCD1_DATA7 /
LCD0_DATA23 / DV1_DATA7 / RxD6 /
TIOC0D / SPDIF_OUT / DV0_DATA15)
11
GND (Vss)
12
GND (Vss)
13
LCD8 (P2_8 / D24 / ET_RXD0 / DV0_DATA8 /
SSISCK0 / LCD0_TCON6 / LCD1_DATA8 /
VIO_D8 / RSPCK4)
14
LCD9 (P2_9 / D25 / ET_RXD1 / DV0_DATA9 /
SSIWS0 / LRXD0 / LCD1_DATA9 / VIO_D9 /
SSL40)
15
LCD10 (P2_10 / D26 / ET_RXD2 /
DV0_DATA10 / SSIRxD0 / LTXD0 /
LCD1_DATA10 / VIO_D10 / MOSI4)
16
LCD11 (P2_11 / D27 / ET_RXD3 /
DV0_DATA11 / SSITxD0 / TIOC1A /
LCD1_DATA11 / VIO_D11 / MISO4)
17
LCD12 (P2_12 / D28 / RSPCK0 /
DV0_DATA12 / SPBIO01_0 / CRx3 / IRQ6 /
LCD1_DATA12 / TIOC1B)
18
LCD13 (P2_13 / D29 / SSL00 / DV0_DATA13 /
SPBIO11_0 / CTx3 / SCK0 / LCD1_DATA13 /
IRQ7)
Note: Bold letters indicate setting functions
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
3-22
R7S72100 CPU (GENMAI) Optional Board
Table 3.1.20
RTK7721000B00000BR
3.
Operational Specification
LCD Panel Connector Pin Assignments 5-2 (J14: ch1, For R0P7724LE0011RL)
Pin No.
Signal Name
Pin No.
Signal Name
19
LCD14 (P2_14 / D30 / MOSI0 / DV0_DATA14 /
SPBIO21_0 / CRx4 / TxD0 / LCD1_DATA14 /
IRQ0)
20
LCD15 (P2_15 / D31 / MISO0 / DV0_DATA15 /
SPBIO31_0 / CAN_CLK / RxD0 /
LCD1_DATA15 / IRQ1)
21
GND (Vss)
22
GND (Vss)
23
LCD16 (P5_9 / WE2/DQMUL / ET_MDC /
DV0_VSYNC / IRQ2 / CRx1 / IERxD /
LCD1_DATA16)
24
LCD17 (P5_10 / WE3/DQMUU/AH /
DV0_HSYNC / CTx1 / IETxD / LCD1_DATA17)
LCD18 (P9_2 / LCD1_DATA18 / SPBCLK_0 /
26
25
LTXD0 / SCK1 / A0)
LCD19 (P9_3 / LCD1_DATA19 / SPBSSL_0 /
TxD1)
27
LCD20 (P9_4 / LCD1_DATA20 / SPBIO00_0 /
RxD1)
28
LCD21 (P9_5 / LCD1_DATA21 / SPBIO10_0 /
SSISCK2 / CTS1 / CS4)
29
LCD22 (P9_6 / LCD1_DATA22 / SPBIO20_0 /
SSIWS2 / RTS1 / CS5)
30
LCD23 (P9_7 / LCD1_DATA23 / SPBIO30_0 /
SSIDATA2 / TIOC1A)
31
GND (Vss)
32
GND (Vss)
33
LCDVSYN (P4_8 / LCD0_DATA16 /
LCD1_TCON3 / SD_CD_0 / MMC_CD /
SSISCK5 / CTx2 / SCK0 / IRQ0)
34
LCDDISP/RS (P4_10 / LCD0_DATA18 /
LCD1_TCON5 / SD_D1_0 / MMC_D1 /
SSIRxD5 / RxD0 / IRQ2)
35
LCDHSYN/CS# (P4_9 / LCD0_DATA17 /
LCD1_TCON4 / SD_WP_0 / SSIWS5 / CRx2 /
TxD0 / IRQ1)
36
NC
37
GND (Vss)
38
GND (Vss)
39
LCDDCK/WR# (P4_12 / LCD0_DATA20 /
LCD1_CLK / SD_CLK_0 / MMC_CLK /
SPBIO10_1 / SSISCK3 / TxD1 / IRQ4)
40
BKPWM
GND (Vss)
42
GND (Vss)
LCDDON
44
NC
41
43
(Connected to +3.3V via 10k Ω resistor)
(Connected to +3.3V via 10k Ω resistor)
45
NC
46
GND (Vss)
47
GND (Vss)
48
SDA0 (P1_7 / SDA3 / DV1_HSYNC / LRXD0 /
IRQ7 / VIO_D13 / DV0_DATA13)
SCL0 (P1_6 / SCL3 / DV1_VSYNC / IERxD /
50
GND (Vss)
49
IRQ6 / VIO_D12 / DV0_DATA12)
51
GND (Vss)
52
TP_IRQ# (P4_11 / LCD0_DATA19 /
LCD1_TCON6 / SD_D0_0 / MMC_D0 /
SSITxD5 / CTx4 / SCK1 / IRQ3)
53
+3.3V
54
+3.3V
55
+3.3V
56
GND (Vss)
57
GND (Vss)
58
+5V
59
+5V
60
+5V
Note: Bold letters indicate setting functions
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
3-23
R7S72100 CPU (GENMAI) Optional Board
3.1.10
RTK7721000B00000BR
3.
Operational Specification
Analog RGB Output Connectors (J15 and J16)
The RTK7721000B00000BR has two analog RGB output connectors (J15 and J16).
Figure 3.1.13 shows the Pinout Diagram of analog RGB Output Connectors, and Table 3.1.21 lists the Analog RGB Output
Connector Pin Assignments.
15 10 5
1 6 11
11 6 1
5 10 15
Figure 3.1.13
Pinout Diagram of analog RGB Output Connectors
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
3-24
R7S72100 CPU (GENMAI) Optional Board
Table 3.1.21
RTK7721000B00000BR
3.
Operational Specification
Analog RGB Output Connector Pin Assignments
Pin No.
Signal Name
J15 (ch0)
J16 (ch1)
1
Video signal (Red)
Video signal (Red)
2
Video signal (Green)
Video signal (Green)
3
Video signal (Blue)
Video signal (Blue)
4
NC (Connected to TP5)
NC (Connected to TP10)
5
GND (Vss)
GND (Vss)
6
GND (Vss)
GND (Vss)
7
GND (Vss)
GND (Vss)
8
GND (Vss)
GND (Vss)
9
NC (Connected to TP6)
NC (Connected to TP11)
10
GND (Vss)
GND (Vss)
11
NC (Connected to TP7)
NC (Connected to TP12)
12
SDA (NC: Connected to TP8)
SDA (NC: Connected to TP13)
13
HSYNC (P11_14 / SPDIF_IN / MOSI1 /
HSYNC (P4_10 / LCD0_DATA18 / LCD1_TCON5 /
LCD0_TCON5 / MMC_D6 / LCD0_TCON0)
SD_D1_0 / MMC_D1 / SSIRxD5 / RxD0 / IRQ2)
VSYNC (P11_13 / CTx1 / SSL10 / LCD0_TCON4 /
VSYNC (P4_14 / LCD0_DATA22 / LCD1_TCON1 /
MMC_D5 / LCD0_TCON1)
SD_D3_0 / MMC_D3 / SPBIO21_1 / SSIRxD3 /
14
TxD2 / IRQ6)
15
SCL (NC: Connected to TP9)
SCL (NC: Connected to TP14)
Note: Bold letters indicate setting functions
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
3-25
R7S72100 CPU (GENMAI) Optional Board
3.1.11
RTK7721000B00000BR
3.
Operational Specification
CMOS Camera Connector (J17)
The RTK7721000B00000BR has a CMOS camera connector (J17).
Figure 3.1.14 shows the Pinout Diagram of CMOS Camera Connector, and Table 3.1.22 lists the CMOS Camera Connector
Pin Assignments.
Top view of
solder side
25
26
Figure 3.1.14
1
2
Pinout Diagram of CMOS Camera Connector
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
J17
3-26
R7S72100 CPU (GENMAI) Optional Board
Table 3.1.22
3.
Operational Specification
CMOS Camera Connector Pin Assignments
Pin No.
1
RTK7721000B00000BR
Signal Name
S_DOUT0 (P10_6 / DV0_DATA2 / TIOC0C /
Pin No.
2
Signal Name
S_DOUT1 (P10_7 / DV0_DATA3 / TIOC0D /
PWM2H / ET_TXD3 / LCD0_DATA16 / VIO_D3)
PWM2G / ET_TXD2 / LCD0_DATA17 /
VIO_D2)
3
S_DOUT2 (P10_8 / DV0_DATA4 / TIOC1A /
4
ET_RXD0 / LCD0_DATA15 / VIO_D4)
5
S_DOUT4 (P10_10 / DV0_DATA6 / TIOC2A /
6
ET_RXD2 / LCD0_DATA13 / VIO_D6)
7
S_DOUT6 (P10_12 / DV0_DATA8 / SSISCK1 /
S_DOUT_LSB0 (P10_4 / DV0_DATA0 /
S_DOUT5 (P10_11 / DV0_DATA7 / TIOC2B /
ET_RXD3 / LCD0_DATA12 / VIO_D7)
8
RSPCK0 / LCD0_DATA11 / VIO_D8)
9
S_DOUT3 (P10_9 / DV0_DATA5 / TIOC1B /
ET_RXD1 / LCD0_DATA14 / VIO_D5)
S_DOUT7 (P10_13 / DV0_DATA9 / SSIWS1 /
SSL00 / LCD0_DATA10 / VIO_D9)
10
S_DOUT_LSB1 (P10_5 / DV0_DATA1 /
TIOC0A / PWM2E / ET_TXD0 /
TIOC0B / PWM2F / ET_TXD1 / LCD0_DATA18 /
LCD0_DATA19 / VIO_D0)
VIO_D1)
11
GND (Vss)
12
GND (Vss)
13
S_LV (P10_2 / DV0_HSYNC / TCLKC /
14
NC
PWM2C / ET_TXEN / LCD0_DATA21 /
VIO_HD)
15
NC
16
RST (Selects RES# or
P10_3 / TCLKD / PWM2D / ET_CRS /
LCD0_DATA20 / VIO_FLD at JP4)
17
S_FV (P10_1 / DV0_VSYNC / TCLKB /
18
PWM2B / ET_TXER / LCD0_DATA22 / VIO_VD)
19
SCL (P1_0 / SCL0 / DV0_DATA16 / TCLKA /
SDA (P1_1 / SDA0 / DV0_DATA17 / TCLKC /
IRQ1 / VIO_HD / DV0_HSYNC)
20
NC
IRQ0 / VIO_VD / DV0_VSYNC)
21
+5V
22
+5V
23
S_PIXCLK (P10_0 / DV0_CLK / TCLKA /
24
GND (Vss)
26
XMCLK (Connects 27MHz oscillator)
PWM2A / ET_TXCLK / LCD0_DATA23 /
VIO_CLK)
25
GND (Vss)
Note: Bold letters indicate setting functions
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
3-27
R7S72100 CPU (GENMAI) Optional Board
3.1.12
RTK7721000B00000BR
3.
Operational Specification
Digital Video Signal Input Connectors (J18 and J19)
The RTK7721000B00000BR has two digital video signal input connectors (J18 and J19).
Figure 3.1.15 shows the Pinout Diagram of Digital Video Signal Input Connectors. Table 3.1.23 and Table 3.1.24 list the
Digital Video Signal Input Pin Assignments.
Top view of
solder side
J19
39
40
Figure 3.1.15
19
2
1
1
2
Pinout Diagram of Digital Video Signal Input Connectors
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
J18
20
3-28
R7S72100 CPU (GENMAI) Optional Board
Table 3.1.23
Signal Name
P10_4 / DV0_DATA0 / TIOC0A / PWM2E /
Pin No.
2
ET_TXD0 / LCD0_DATA19 / VIO_D0
3
3.
Operational Specification
Digital Video Signal Input Connector Pin Assignments 1 (J18: ch0)
Pin No.
1
RTK7721000B00000BR
P10_6 / DV0_DATA2 / TIOC0C / PWM2G /
Signal Name
P10_5 / DV0_DATA1 / TIOC0B / PWM2F /
ET_TXD1 / LCD0_DATA18 / VIO_D1
4
ET_TXD2 / LCD0_DATA17 / VIO_D2
P10_7 / DV0_DATA3 / TIOC0D / PWM2H /
ET_TXD3 / LCD0_DATA16 / VIO_D3
5
+3.3V
6
7
P10_9 / DV0_DATA5 / TIOC1B / ET_RXD1 /
8
P10_8 / DV0_DATA4 / TIOC1A / ET_RXD0 /
LCD0_DATA15 / VIO_D4
LCD0_DATA14 / VIO_D5
9
P10_11 / DV0_DATA7 / TIOC2B / ET_RXD3 /
P10_10 / DV0_DATA6 / TIOC2A / ET_RXD2 /
LCD0_DATA13 / VIO_D6
10
+5V
LCD0_DATA12 / VIO_D7
11
P10_12 / DV0_DATA8 / SSISCK1 / RSPCK0 /
12
LCD0_DATA11 / VIO_D8
13
P10_14 / DV0_DATA10 / SSIRxD1 / MOSI0 /
14
LCD0_DATA9 / VIO_D10
15
+3.3V
P10_13 / DV0_DATA9 / SSIWS1 / SSL00 /
LCD0_DATA10 / VIO_D9
P10_15 / DV0_DATA11 / SSITxD1 / MISO0 /
LCD0_DATA8 / VIO_D11
16
P11_0 / DV0_DATA12 / TIOC4A / SCK6 /
LCD0_DATA7 / VIO_D12
17
P11_1 / DV0_DATA13 / TIOC4B / TxD6 /
18
LCD0_DATA6 / VIO_D13
19
P11_3 / DV0_DATA15 / TIOC4D /
P11_2 / DV0_DATA14 / TIOC4C / RxD6 /
LCD0_DATA5 / VIO_D14
20
+5V
22
P11_5 / DV0_DATA17 / SD_WP_0 / SSIWS4 /
LCD0_DATA4 / VIO_D15
21
P11_4 / DV0_DATA16 / SD_CD_0 / SSISCK4 /
MMC_CD / LCD0_DATA3
23
P11_6 / DV0_DATA18 / SD_D1_0 / SSIDATA4 /
LCD0_DATA2
24
P11_7 / DV0_DATA19 / SD_D0_0 / CTS5 /
P11_8 / DV0_DATA20 / SD_CLK_0 / RTS5 /
MMC_D1 / LCD0_DATA1
MMC_D0 / LCD0_DATA0
25
GND (Vss)
26
27
P11_9 / DV0_DATA21 / SD_CMD_0 / SCK5 /
28
MMC_CLK / LCD0_TCON6
MMC_CMD / LCD0_TCON5
29
P11_11 / DV0_DATA23 / SD_D2_0 / RxD5 /
P11_10 / DV0_DATA22 / SD_D3_0 / TxD5 /
MMC_D3 / LCD0_TCON4
30
GND (Vss)
MMC_D2 / LCD0_TCON3
31
NC
32
P10_0 / DV0_CLK / TCLKA / PWM2A /
ET_TXCLK / LCD0_DATA23 / VIO_CLK
33
P10_1 / DV0_VSYNC / TCLKB / PWM2B /
34
ET_TXER / LCD0_DATA22 / VIO_VD
P10_2 / DV0_HSYNC / TCLKC / PWM2C /
ET_TXEN / LCD0_DATA21 / VIO_HD
35
GND (Vss)
36
NC
37
NC
38
NC
39
NC
40
GND (Vss)
Note: Bold letters indicate setting functions
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
3-29
R7S72100 CPU (GENMAI) Optional Board
Table 3.1.24
3
Signal Name
P5_0 / TXCLKOUTP / LCD1_DATA0 /
Pin No.
2
TIOC0B / SSL30
P5_2 / TXOUT2P / LCD1_DATA2 /
4
TIOC3C / MISO3
+3.3V
6
P5_4 / TXOUT1P / LCD1_DATA4 /
8
13
P5_6 / TXOUT0P / LCD1_DATA6 /
+3.3V
P5_5 / TXOUT1M / LCD1_DATA5 /
LCD0_DATA21 / DV1_DATA5 / AUDIO_XOUT /
TIOC0C / FCE / DV0_DATA13
10
P5_7 / TXOUT0M / LCD1_DATA7 /
LCD0_DATA22 / DV1_DATA6 / TxD6 / IRQ6 /
LCD0_DATA23 / DV1_DATA7 / RxD6 /
SPDIF_IN / DV0_DATA14
TIOC0D / SPDIF_OUT / DV0_DATA15
+5V
12
P1_5 / SDA2 / DV1_CLK / CRx4 / IRQ5 /
14
VIO_CLK / LCD1_EXTCLK
15
P5_3 / TXOUT2M / LCD1_DATA3 /
LCD0_DATA19 / DV1_DATA3 / TxD3 /
TIOC3D / DV0_DATA12
11
P5_1 / TXCLKOUTM / LCD1_DATA1 /
LCD0_DATA17 / DV1_DATA1 / RxD4 /
LCD0_DATA20 / DV1_DATA4 / RxD3 /
9
Signal Name
TIOC0A / RSPCK3
TIOC1B / MOSI3
7
Operational Specification
LCD0_DATA16 / DV1_DATA0 / TxD4 /
LCD0_DATA18 / DV1_DATA2 / SCK3 /
5
3.
Digital Video Signal Input Connector Pin Assignments 2 (J19: ch1)
Pin No.
1
RTK7721000B00000BR
NC
+5V
P1_6 / SCL3 / DV1_VSYNC / IERxD / IRQ6 /
VIO_D12 / DV0_DATA12
16
P1_7 / SDA3 / DV1_HSYNC / LRXD0 / IRQ7 /
VIO_D13 / DV0_DATA13
17
GND (Vss)
18
GND (Vss)
19
NC
20
NC
Note: Bold letters indicate setting functions.
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
3-30
R7S72100 CPU (GENMAI) Optional Board
3.2
RTK7721000B00000BR
3.
Operational Specification
Operation Parts Layout
Figure 3.2.1
SW1 to SW13: Key input switches
JP1: SCI mode select jumper
RTK7721000B00000BR Operation Parts Layout 1 (Top View of Component Side)
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
JP5: IrRXD connection jumper
JP3: LRXD0 connection jumper
JP2: IERxD connection jumper
SW14:
DIP switch for video DAC setting
Figure 3.2.1 and Figure 3.2.2 show the RTK7721000B00000BR Operation Parts Layouts.
3-31
Figure 3.2.2
Operational Specification
JP7: IERxD and LCD1_DATA16
connection jumper
3.
RTK7721000B00000BR Operation Parts Layout 2 (Top View of Solder Side)
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
RTK7721000B00000BR
JP6: LCD1_DATA18 connection jumper
JP4: CMOS camera reset select jumper
R7S72100 CPU (GENMAI) Optional Board
3-32
R7S72100 CPU (GENMAI) Optional Board
3.2.1
RTK7721000B00000BR
3.
Operational Specification
Jumpers (JP1 to JP7)
The RTK7721000B00000BR has seven jumpers for system setting.
Figure 3.2.3 shows the Jumper Layout for RTK7721000B00000BR System Setting, and Table 3.2.1 lists the Jumper Setting
for Switching Multifunctional Pins (JP1 to JP7).
JP3
Top view of
component side
JP2
1 3
JP5
JP1
Top view of
solder side
JP4
1 3
JP7
JP6
Figure 3.2.3
Jumper Layout for RTK7721000B00000BR System Setting
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
3-33
R7S72100 CPU (GENMAI) Optional Board
Table 3.2.1
RTK7721000B00000BR
3.
Operational Specification
Jumper Setting for Switching Multifunctional Pins (JP1 to JP7)
Jumper
Setting
JP1
Short
Connects SCI_TXD0 and SCI_RXD0 as the smart card interface mode
SCI mode select
Open
Disconnects SCI_TXD0 and SCI_RXD0 as the serial communication interface mode
JP2
1-2
Connected to IEBus transceiver (U4) as IERxD input pin
IERxD /
2-3
Connected to LCD output connector 2 (J12 to J14) and video DAC 2 (U10) as
LCD1_DATA16
Function
LCD1_DATA16 output pin
JP3
Short
Connected to LIN transceiver (U5) as LRXD0 input pin
LRXD0 /
Open
Connected to LCD output connector 2 (J12 to J14) and video DAC 2 (U10) as
LCD1_DATA10
JP4
LCD1_DATA10 output pin
1-2
of CMOS camera connector
CMOS camera
reset control
Connects RES signal generated on the RTK772100BC00000BR to the reset signal
2-3
Connects P10_3 pin to the reset signal of CMOS camera connector (J17)
JP5
Short
Connected to IrDA module (U3) as SCI_RXD0 input pin
SCI_RXD0/
Open
Connected to SIM card slot (J2) as SCI_RXD0 input pin
RxD3
JP6
LCD1_DATA18 /
SPBCLK_0
JP7
Connected to UART connector (J3) as RxD3 input pin
Short
LCD1_DATA18 output pin
Open
LCD1_DATA16
Connected to serial flash memory 1 (U6) and 2 (U7) on the RTK772100BC00000BR
as SPBCLK_0 output pin
Short
Connected to IEBus transceiver (U4) as IERxD input pin
Connected to LCD output connector 2 (J12 to J14) and video DAC 2 (U10) as
ET_MDC /
IERxD /
Connected to LCD output connector 2 (J12 to J14) and video DAC 2 (U10) as
LCD1_DATA16 output pin
Open
Connected to Ethernet PHY (U20) on the RTK772100BC00000BR as ET_MDC
output pin
Indicates initial setting.
Note: The power of the board should be off when changing the jumper setting.
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
3-34
R7S72100 CPU (GENMAI) Optional Board
3.2.2
RTK7721000B00000BR
3.
Operational Specification
Switches
SW14
←
OFF
Closeup
D
Top view of
component side
Figure 3.2.4
SW1
SW3
SW5
SW7
SW9
SW11
SW13
SW2
SW4
SW6
SW8
SW10
SW12
RTK7721000B00000BR Switch Layout
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
B
→
←
8
C
1
ON
→
A
The RTK7721000B00000BR has 14 switches.
Figure 3.2.4 shows the RTK7721000B00000BR Switch Layout. Table 3.2.2 lists the RTK7721000B00000BR Switches,
and Table 3.2.3 lists the Function Description of DIP Switch for I/F Setting (SW14).
3-35
R7S72100 CPU (GENMAI) Optional Board
Table 3.2.2
Function
SW1 to SW13
SW14
Video DAC 1
Operational Specification
Remarks
DIP switches for key input
Refer to Section 2.15 for more details
DIP switch for I/F setting (8/package)
Refer to Table 3.2.3 for more details.
Function Description of DIP Switch for I/F Setting (SW14)
No.
Video DAC 2
3.
RTK7721000B00000BR Switches
No.
Table 3.2.3
RTK7721000B00000BR
Setting
Function
SW14-1
OFF
BLANK = "H"
Normal analog output
BLANK pin setting
ON
BLANK = "L"
Fix analog outputs (IOR, IOB, IOG) to blanking level
SW14-2
OFF
SYNC = "H"
Do not remove 40IRE current source
SYNC pin setting
ON
SYNC = "L"
Remove 40IRE current source
SW14-3
OFF
PSAVE = "H"
Normal operating mode
PSAVE pin setting
ON
PSAVE = "L"
Power down mode
SW14-4
OFF
BLANK = "H"
Normal analog output
BLANK pin setting
ON
BLANK = "L"
Fix analog outputs (IOR, IOB, IOG) to blanking level
SW14-5
OFF
SYNC = "H"
Do not remove 40IRE current source
SYNC pin setting
ON
SYNC = "L"
Remove 40IRE current source
SW14-6
OFF
PSAVE = "H"
Normal operating mode
ON
PSAVE = "L"
Power down mode
OFF
SCI# / CD =
Connected to CD deck connector (J8)
PSAVE pin setting
SW14-7
P3_[6:3] selection for
"H"
connection destination
ON
SW14-8
OFF
TP15 = "H"
TP15
ON
TP15 = "L"
SCI# / CD =
Connected to SIM card slot (J2), IrDA module (U3) and UART
"L"
connector (J3)
Indicates initial setting.
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
3-36
R7S72100 CPU (GENMAI) Optional Board
3.3
RTK7721000B00000BR
3.
Operational Specification
Dimensions
Figure 3.3.1 and Figure 3.3.2 show the RTK7721000B00000BR Dimensions (Top View of Component Side). Figure 3.3.3
shows the RTK7721000B00000BR Dimensions (Perspective View of Component Side).
[Top View of Component Side]
Figure 3.3.1
RTK7721000B00000BR Dimensions 1 (Top View of Component Side1)
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
Unit: mm
3-37
R7S72100 CPU (GENMAI) Optional Board
RTK7721000B00000BR
3.
Operational Specification
[Top View of Component Side]
Figure 3.3.2
RTK7721000B00000BR Dimensions 2 (Top View of Component Side 2)
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
Unit: mm
3-38
R7S72100 CPU (GENMAI) Optional Board
RTK7721000B00000BR
[Perspective View of Component Side]
Figure 3.3.3
Operational Specification
Unit: mm
RTK7721000B00000BR Dimensions 3 (Perspective View of Component Side)
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
3.
3-39
R7S72100 CPU (GENMAI) Optional Board
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
RTK7721000B00000BR
3.
Operational Specification
3-40
R7S72100 CPU (GENMAI) Optional Board RTK7721000B00000BR
Appendix
Appendix RTK7721000B00000BR Schematics
R20UT2696EJ0005 Rev.0.05
Sep. 06, 2013
Appendix-1
1
2
3
4
5
R7S72100 Optional board RTK7721000B00000BR SCHEMATICS
for RTK772100FC00000BR & RTK772100BC00000BR
A
A
TITLE
PAGE
Index
Ext. Connector with CPU board, Power
SCIc(SIM, IrDA, UART), IEBus, LIN
Audio-DAC, CD, HCI, Push-SW
LCD
Video-Encoder
CMOS, DV
B
Note:
1
2
3
4
5
6
7
Digital GND (GND)
Analog GND (AVss)
B
Not mounted
12VCC = Digital 12V (System Power)
8VCC = Digital 8V for CD deck
5VCC = Digital 5V
3VCC = Digital 3.3V
AVcc = Analog 3.3V for R7S72100 ADC
AN3V = Analog 3.3V for AK4353, ADV7123
R
RA
C
CE
CP
C
=
=
=
=
=
Fixed Resistors
Resistor Array
Ceramic Caps
Tantalum Electrolytic Caps
Decoupling Caps
C
D
D
CHANGE
Renesas Solutions Corp.
DRAWN
SCALE
DATE
1
2
CHECKED
DESIGNED
INDEX
( 1
/ 7
D-RTK7721000B00000BR_C-A
13-07-02
3
APPROVED
RTK7721000B00000BR
4
5
)
1
2
3
4
5
[4,5,7] P1_[15:0]
[3,4] P3_[15:0]
[4,5,6,7]
P11_[15:0]
[5,6,7] P10_[15:0]
[4] P7_[8:0]
[3,5,6,7]
[4,5,6] P4_[15:0]
P5_[10:0]
[3,4,5,6]
P2_[15:0]
[5,6] P9_[7:2]
P3_9
P3_11
3VCC
CN8
3VCC
HIF3FB-20DA-2.54DSA
HRS
2
4
6
8
10
12
14
16
18
20
A
5VCC
P3_8
P3_10
P3_12
P3_14
3VCC
P4_0
P4_2
P10_4
P10_6
P2_13
P2_15
P4_4
P4_6
P1_1
P1_3
P1_5
P1_7
P2_12
P2_14
B
P1_0
P1_2
P1_4
P1_6
0.1µF
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
CP24
P10_9
P10_11
P10_13
P10_15
P4_9
P4_11
P4_13
P4_15
P2_1
P2_3
P2_5
P2_7
P2_9
P2_11
CN7
SSW-117-01-L-D
Samtec
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
0.1µF
CP22
P9_2
P9_4
P9_6
0.1µF
P5_9
[4] AUDIO_XTAL1
CP23
1
3
5
7
9
11
13
15
17
19
0.1µF
0.1µF
0.1µF
0.1µF
P1_9
P11_0
P11_2
0.1µF
P11_1
P11_3
JP6
HWP-2P-G
P1_11
CP21
P9_3
P9_5
P9_7
0.1µF
P5_10
JP7
HWP-2P-G
P4_5
P4_7
0.1µF
0.1µF
P5_8
P10_5
P10_7
P5_0
P5_2
P5_4
P5_6
CP17
B
3VCC
CP15
CP16
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
P5_1
P5_3
P5_5
P5_7
P1_13
P10_2
P10_0
0.1µF
0.1µF
0.1µF
5VCC 3VCC
P4_1
P4_3
CN9
SSW-115-01-L-D
Samtec
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
CN6
SSW-115-01-L-D
Samtec
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
P1_15
P3_4
P3_6
CP7
CP8
CP9
CP10
P10_3
P10_1
P3_0
P3_2
CP6
P11_14
P11_12
P7_8
P7_6
P7_4
P7_2
P7_0
CN5
AVcc VBUS 12VCC
HIF3FB-20DA-2.54DSA
HRS
2
4
6
8
P1_14
10
12
P1_12
14
16
P1_10
18
20
P1_8
0.1µF
P3_5
P3_7
1
3
5
7
9
11
13
15
17
19
12VCC VBUS AVcc
RES# [4,7]
CP5
P3_1
P3_3
P11_6
P11_4
P3_13
P3_15
3VCC
CN4
HIF3FB-20DA-2.54DSA
HRS
2
4
6
8
10
12
14
16
18
20
0.1µF
0.1µF
0.1µF
0.1µF
P11_10
P11_8
CP13
CP14
CP11
CP12
0.1µF
0.1µF
P7_7
P7_5
P7_3
P7_1
NMI
CP1
CP2
CP3
CP4
P11_15
P11_13
CKIO_CN
0.1µF
0.1µF
P11_7
P11_5
1
3
5
7
9
11
13
15
17
19
3VCC
0.1µF
P11_11
P11_9
CN2
HIF3FB-30DA-2.54DSA
HRS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
CP19
CP20
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
CP18
3VCC
A
AUDIO_XTAL2 [4]
P10_8
P10_10
P10_12
P10_14
P4_8
P4_10
P4_12
P4_14
P2_0
P2_2
P2_4
P2_6
P2_8
P2_10
C
C
Board fixed hole. (M3)
U1
LM20242
TI
CP26
0.1µF
MH5
3VCC
HOLE
HOLE
MH2
MH6
HOLE
HOLE
MH3
MH7
HOLE
HOLE
MH4
MH8
HOLE
HOLE
5VCC
12VCC
TP3
GND
CP29
1µF
J1
XG8S-0331
OMRON
0.1µF
0.1µF
0.1µF
0Ω
CQ9
CQ10
CQ11
R4
0.1µF
0.1µF
0.1µF
AGND-DGND
CQ6
CQ7
CQ8
18
3
0.1µF
0.1µF
R3
11.8kΩ
CQ4
CQ5
RQ1
RQ2
RQ3
17
2
Anti-resonant circuit
for Connect to CPU-board x 4
MH1
0.1µF
0.1µF
0.1µF
0.0068µF
C1
0.0033µF
R6
R7
CP28
22µF/50V
for Corner x 4
TP2
AN3V
for Connect to R0P7724LE0011RL
1
2
3
MH9
C2
VCC
PGOOD
R1
107kΩ
AN3V
L2
BLM21PG300SN1D
CQ1
CQ2
CQ3
EN
1
4
16.2kΩ-1% 20
110kΩ-1% 9
10
11
12
21
19
BOOT
FB
CP27
0.1µF
3VCC
TP1
8V
49.9kΩ
R2
_10kΩ
SW1
SW2
SW3
SW4
7
8
13
14
8VCC
R5
VIN1
VIN2
VIN3
VIN4
SS/TRK
COMP
RT
GND1
GND2
GND3
AGND
EP
CP25
22µF/50V
5
6
15
16
L1
SLF7055T-6R8N2R8
TDK
4.7Ω
4.7Ω
4.7Ω
12V -> 8V
12VCC
HOLE
D
D
CHANGE
Renesas Solutions Corp.
DRAWN
CHECKED
DESIGNED
APPROVED
RTK7721000B00000BR
Ext. Connector, Power
( 2
/ 7
SCALE
DATE
1
2
D-RTK7721000B00000BR_C-A
13-07-02
3
4
5
)
1
2
3
4
5
TP4
P3_4
7
P3_5
9
P3_6
12
3
5
1B2
2B1
2A
2B2
3B1
3A
3B2
4B1
4A
6
11
P3_4/SSISCK1
10
14
P3_5/SSIWS1
13
4B2
3VCC
P3_3/SSL40 [4]
P3_6/SSIRxD1
[4]
[4]
OE
S
1
Vcc
R8
R9
C2
P3B_6
3VCC
CD deck
8
GND
CLK
I/O
3VCC
5VCC
C1
C6
Vcc
Vpp
RST
P3B_5
CP30
0.1µF
C5
GND
A
CP31
0.1µF
IrDA Module
15
16
P3B_3
[4]
MUX
CP32
0.1µF
P3_3/RES-Ctrl
P3B_4
J2
FMS006Z-2001-1
Yamaichi
C3
C7
C4
C8
P3_4
1A
P3B_4
P3B_5
P3B_6
[6] SW14-7
P3B_5
P3B_6
JP5
HWP-2P-G
U3
RPM871
ROHM
7
6
8
5
3VCC
TXD
RXD
Vcc
LEDA
PDN
GND
GND
3
4
1
CP33
1µF
R11
2
22kΩ
P3_5/IrTXD
P3_6/IrRXD
NC
4
P3_4/SCIc_SCK0
P3_5/SCIc_TXD0
P3_6/SCIc_RXD0
7.5Ω, 1/4W
P3_3
P3B_3
R10
A
2
1B1
SIM Card
P3B_[6:3]
JP1
U2
SN74CB3Q3257
Texas Instruments
RFU1
RFU2
SCIc / CD#
[2,4] P3_[15:0]
22kΩ
1kΩ
HWP-2P-G
3VCC
UART Connector
J3
S5B-XH-A
JST
5VCC
B
1
2
3
4
5
P3B_4
P3B_5
P3B_6
B
BxB-XH-A : Top-type
SxB-XH-A : Side-type -> Decide by Parts-layout
CP34
0.1µF
P3_4/SCK3
P3_5/TxD3
P3_6/RxD3
P5_[10:0]
R14
R15
5VCC
Vcc
7
CP35
0.1µF
10Ω
10Ω
C
R16
4
STB
R127
6
5
0.1µF
8
J4
S4B-XH-A
JST
1
2
3
4
CP36
3
BUS+
BUS-
R
_10pF
2
C
S1
S2
_10pF
P5_9
2
22kΩ
P5_9/IERxD
1
3
C4
JP2
HWP-3P-G
1
IEBus
5VCC
C3
P5_10
U4
R2A11210SP
Renesas
GND
P5_10/IETxD
R12
R13
[2,5,6,7]
62Ω
22kΩ
1kΩ
3VCC
3VCC
1kΩ
5VCC
5VCC
7
CP38
0.1µF
R21
BAT
0.1µF
SLP
WAKE
INH
1
2
3
6
CP37
LIN
LIN
J5
S3B-XH-A
JST
5VCC
_10pF
R19
2
3
8
TXD
RXD
R20
1kΩ
C5
P2_11
4
1
JP3
HWP-2P-G
GND
P2_11
U5
MAX13020
MAXIM
5
P2_10
P2_9
22kΩ
P2_10/LTXD0
P2_9/LRXD0
R18
P2_[15:0]
R17
[2,4,5,6]
_22kΩ
4.99kΩ
5VCC
D
D
CHANGE
Renesas Solutions Corp.
DRAWN
CHECKED
DESIGNED
APPROVED
RTK7721000B00000BR
SCIc, IEB, LIN
( 3
/ 7
SCALE
DATE
1
2
D-RTK7721000B00000BR_C-A
13-07-02
3
4
5
)
5
4
3
2
1
[2,5,6] P4_[15:0]
3VCC
[2,5,7] P1_[15:0]
Audio DAC1
U6
AK4353VF
AKM
P7_6
P7_5
P4_15
7
15
10
P7_6/CTS7
P7_5/RxD7
P1_4/SCL2
P1_4
11
P1_5/SDA2
P1_5
12
I2C
CSN
DZF
NC
SCL/CCLK
TX
SDA/CDTI
TTL
CAD1
CAD0
4
TST
24
CE1
10µF/16V
J6
HSJ1456-010320
JALCO
CE2
10µF/16V
R26
220Ω
2
4
CE3
10µF/16V
R28
220Ω
3
1
3VCC
D
23
2
14
13
CP44
0.1µF
CE4
10µF/16V
AN3V
+
+
3VCC 3VCC 8VCC
18
SDTI
DVSS
0.1µF
3VCC
CP43
0.1µF
3VCC
AOUTR
+
P4_15/SSITxD3
LRCK
19
27kΩ
27kΩ
P7_8/Port
P2_4/SSISCK5
P2_6/SSIRxD5
8
AOUTL
+
P3_1/AUDIO_CLK
P7_8
P2_4
P2_6
P4_13
MCKI
MCKO
BICK
20
+
P3_1
P4_12
P4_13/SSIWS3
CP39
0.1µF
VCOM
R30
R31
18Ω
P4_12/SSISCK3
17
16
CP40
3VCC
R27
22Ω
R29
CP42
P7_7
P7_4
0.1µF
P7_7/RTS7
P7_4/TxD7
0.1µF
P2_5
P2_7
CP41
P1_0
P1_1
P2_5/SSIWS5
P2_7/SSITxD5
J7
HIF3FC-20PA-2.54DSA
HRS
2
4
6
8
10
12
14
16
18
20
5
1
6
R25
22Ω
PDN
AVDD
1
3
5
7
9
11
13
15
17
19
[2] AUDIO_XTAL2
[2] AUDIO_XTAL1
_18pF
D
P1_0/SCL0
P1_1/SDA0
3VCC 5VCC
HCI
C6
5VCC 3VCC
9
AVSS
P4_14
22
R22
R23
R24
[2,3] P3_[15:0]
DVDD
P2_[15:0]
21
P11_[15:0]
[2] P7_[8:0]
3
[2,3,5,6]
22kΩ
22kΩ
22kΩ
[2,5,6,7]
CP45
0.1µF
CE5
10µF/16V
P1_4
11
P1_5/SDA2
P1_5
12
R54
17
16
3VCC
P1_8
R55
4.7kΩ
B
3
4
R57
3.16kΩ
1
2
3
4
R58
6.98kΩ
1
2
3
4
R59
18.7kΩ
1
2
3
4
NC
SCL/CCLK
TX
SDA/CDTI
TTL
CAD1
CAD0
CP49
0.1µF
CE9
10µF/16V
TST
24
CE6
10µF/16V
J9
HSJ1456-010320
JALCO
CE7
10µF/16V
R43
220Ω
2
4
CE8
10µF/16V
R45
220Ω
3
1
3VCC
27kΩ
27kΩ
DZF
23
2
14
13
AN3V
+
R56
1.18kΩ
1
2
+
P1_8/AN0
I2C
CSN
4
AVcc
18
SDTI
DVSS
22kΩ
AOUTR
19
R52
R53
15
10
P1_4/SCL2
LRCK
+
7
20
+
8
P11_6
AOUTL
+
P11_5
P11_6/SSIDATA4
VCOM
MCKI
MCKO
BICK
AVDD
P11_5/SSIWS4
PDN
22
5
1
6
AVSS
P11_4
C
CP46
0.1µF
21
R42
R41
9
P11_4/SSISCK4
DVDD
22kΩ
22kΩ
U7
AK4353VF
AKM
3
C8
IIS_BCK
IIS_LRCK
IIS_DATA
BLKCK
TRANS
_22kΩ
22Ω
22Ω
22Ω
22Ω
22Ω
CDFS
CDSI
CDCK
CDSO
0.1µF
22Ω
R46
R47
R48
R50
R51
Audio DAC2
CDRST
CP48
R44
CP47
P3_1/IRQ6
P1_12/trans
[3] P3_4/SSISCK1
[3] P3_5/SSIWS1
[3] P3_6/SSIRxD1
P3_1
P1_12
_10pF
P4_2
P4_0
P4_3
0.1µF
[3] P3_3/SSL40
P4_2/MOSI4
P4_0/RSPCK4
P4_3/MISO4
FLAG6
_18pF
22Ω
[2,7] RES#
C7
R40
C
3VCC
R49
22kΩ
22kΩ
22kΩ
22kΩ
J8
IMSA-9617S-22
IRISO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
R39
P1_13
P1_13/flag6
R36
R37
R38
R32
R33
R34
R35
22kΩ
22kΩ
22kΩ
22kΩ
CD Deck
CP50
0.1µF
CE10
10µF/16V
B
AVcc
SW1
B3S-1000
P1_9/AN1
P1_9
SW2
B3S-1000
SW3
B3S-1000
SW4
B3S-1000
R60
4.7kΩ
R61
1.18kΩ
1
2
3
4
R62
3.16kΩ
1
2
3
4
R63
6.98kΩ
1
2
3
4
R64
18.7kΩ
1
2
3
4
AVcc
P1_10/AN2
P1_10
R65
4.7kΩ
SW5
B3S-1000
R66
1.18kΩ
1
2
SW6
B3S-1000
3
4
R67
3.16kΩ
1
2
SW7
B3S-1000
3
4
R68
6.98kΩ
1
2
SW8
B3S-1000
3
4
R69
18.7kΩ
1
2
3
4
AVcc
SW9
B3S-1000
P1_11/AN3
R71
931Ω
R73
2.37kΩ
R74
4.7kΩ
P1_11
SW13
SKRHABE010
1 ALPS
4
2
5
3
6
SW10
B3S-1000
SW11
B3S-1000
SW12
B3S-1000
R70
4.7kΩ
R72
9.31kΩ
R75
23.7kΩ
A
A
CHANGE
Renesas Solutions Corp.
DRAWN
CHECKED
DESIGNED
APPROVED
RTK7721000B00000BR
DAC, CD, HCI, Push-SW
( 4
/ 7
SCALE
DATE
5
4
D-RTK7721000B00000BR_C-A
13-07-02
3
2
1
)
5
4
3
2
1
[2,4,7] P1_[15:0]
[2,4,6,7]
P11_[15:0]
P11_[15:0]
P10_[15:0]
[2,6,7] P10_[15:0]
3VCC
5VCC
3VCC
P1_1
P1_0
P11_13
P11_14/LCD0_TCON0
P11_14
10kΩ
_10kΩ
_10kΩ
R77
R78
P10_2
P10_0
P11_14/LCD0_TCON0
P11_12/LCD0_TCON2
P11_9/LCD0_TCON5
P11_15/LCD0_CLK
P11_14
P11_12
P11_9
P11_15
0.1µF
P1_1/SDA0
P1_0/SCL0
P11_13/LCD0_TCON1
P10_2/LCD0_DATA21
P10_0/LCD0_DATA23
0.1µF
P11_15
P10_10
P10_8
P10_7
P10_5
CP54
P11_15/LCD0_CLK
P10_10/LCD0_DATA13
P10_8/LCD0_DATA15
P10_7/LCD0_DATA16
P10_5/LCD0_DATA18
CP53
P11_12
P11_11
P11_10
P11_2
P11_0
P10_15
P10_13
J11
3VCC 5VCC
HIF3FC-40PA-2.54DSA
HRS
2
P11_6
4
P11_4
6
P11_3
8
P11_1
10
12
P10_14
14
P10_12
16
P10_11
18
P10_9
20
22
P10_6
24
P10_4
26
P10_3
28
P10_1
30
32
P11_13
34
P11_11
36
P11_10
38
P11_8
40
0.1µF
P11_12/LCD0_TCON2
P11_11/LCD0_TCON3
P11_10/LCD0_TCON4
P11_2/LCD0_DATA5
P11_0/LCD0_DATA7
P10_15/LCD0_DATA8
P10_13/LCD0_DATA10
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
CP52
P11_1
P11_0
P10_15
P10_14
P10_13
P10_12
P10_11
P10_10
P10_9
P10_8
P10_7
P10_6
P11_7
P11_5
0.1µF
P11_1/LCD0_DATA6
P11_0/LCD0_DATA7
P10_15/LCD0_DATA8
P10_14/LCD0_DATA9
P10_13/LCD0_DATA10
P10_12/LCD0_DATA11
P10_11/LCD0_DATA12
P10_10/LCD0_DATA13
P10_9/LCD0_DATA14
P10_8/LCD0_DATA15
P10_7/LCD0_DATA16
P10_6/LCD0_DATA17
5VCC 3VCC
P11_7/LCD0_DATA0
P11_5/LCD0_DATA2
CP51
P11_7
P11_6
P11_5
P11_4
P11_3
P11_2
J10
XF2J-4024-12A
OMRON
3.3V
3.3V
3.3V
GND
GND
B0
B1
B2
B3
B4
B5
GND
G0
G1
G2
G3
G4
G5
R0
R1
R2
R3
R4
R5
GND
DE
HSYNC(NC)
VSYNC(NC)
GND
LCDCLK
GND
+5V
+5V
+5V
NC
SDA
SCL
INT
NC
RESET
_18pF
P11_7/LCD0_DATA0
P11_6/LCD0_DATA1
P11_5/LCD0_DATA2
P11_4/LCD0_DATA3
P11_3/LCD0_DATA4
P11_2/LCD0_DATA5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
C9
D
R76
for LCD-KIT-B01
P11_6/LCD0_DATA1
P11_4/LCD0_DATA3
P11_3/LCD0_DATA4
P11_1/LCD0_DATA6
D
P10_14/LCD0_DATA9
P10_12/LCD0_DATA11
P10_11/LCD0_DATA12
P10_9/LCD0_DATA14
P10_6/LCD0_DATA17
P10_4/LCD0_DATA19
P10_3/LCD0_DATA20
P10_1/LCD0_DATA22
P11_13/LCD0_TCON1
P11_11/LCD0_TCON3
P11_10/LCD0_TCON4
P11_8/LCD0_TCON6
[2,3,6,7]
P5_[10:0]
[2,3,4,6]
P2_[15:0]
0.1µF
8
4
X1
_SG-8002DC
VCC OUT
GND OE
XR2A-0811-N
[2,6] P9_[7:2]
P1_[15:0]
P1_[15:0]
P5_[10:0]
P5_[10:0]
P2_[15:0]
P2_[15:0]
P9_[7:2]
P9_[7:2]
P4_[15:0]
[2,4,6] P4_[15:0]
3VCC
5
1
P5_8
R79
18Ω
P5_8/LCD0_EXTCLK
C
CP57
CP55
CP56
C10
0.1µF
0.1µF
_18pF
3VCC
C
5VCC
P4_[15:0]
3VCC
3VCC
_10kΩ
P4_12
NC
P1_6
SCL0
P5_1/LCD1_DATA1
P5_3/LCD1_DATA3
P5_5/LCD1_DATA5
P5_7/LCD1_DATA7
P2_9
P2_11
P2_13
P2_15
P2_9/LCD1_DATA9
P2_11/LCD1_DATA11
P2_13/LCD1_DATA13
P2_15/LCD1_DATA15
P4_10
B
3VCC
P5_10
P9_3
P9_5
P9_7
LCDDISP(DE)
P5_10/LCD1_DATA17
P9_3/LCD1_DATA19
P9_5/LCD1_DATA21
P9_7/LCD1_DATA23
P4_10/LCD1_TCON5
NC
BKPWM
0.1µF
0.1µF
0.1µF
CP64
CP65
NC
CP63
FG
P5_1
P5_3
P5_5
P5_7
10kΩ
R83
10kΩ
P4_8
P4_9
LCDVSYN
LCDHSYN
CP61
CP60
P5_9
P9_2
P9_4
P9_6
LCDDON
P1_6/SCL3
CP59
P2_8
P2_10
P2_12
P2_14
R85
0.1µF
P4_10
P4_12
0.1µF
P4_10/LCD1_TCON5
P4_12/LCD1_CLK
0.1µF
P4_13
P4_15
P9_5
P9_7
0.1µF
P9_2
P9_5/LCD1_DATA21
P9_7/LCD1_DATA23
P4_13/LCD1_TCON0
P4_15/LCD1_TCON2
P2_9/LCD1_DATA9
P2_11/LCD1_DATA11 P2_8/LCD1_DATA8
P2_12/LCD1_DATA12 P2_10/LCD1_DATA10
P2_14/LCD1_DATA14 P2_12/LCD1_DATA12
P2_14/LCD1_DATA14
P5_10/LCD1_DATA17
P9_3/LCD1_DATA19 P5_9/LCD1_DATA16
P9_4/LCD1_DATA20 P9_2/LCD1_DATA18 3VCC
P9_6/LCD1_DATA22 P9_4/LCD1_DATA20
P9_6/LCD1_DATA22
P4_14/LCD1_TCON1
P4_8/LCD1_TCON3
P4_8/LCD1_TCON3
P4_9/LCD1_TCON4
P4_9/LCD1_TCON4
P4_11/LCD1_TCON6
P4_12/LCD1_CLK
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
R84
_10kΩ
R82
P9_2/LCD1_DATA18
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61 FG
P5_0
P5_2
P5_4
P5_6
P5_0/LCD1_DATA0
P5_2/LCD1_DATA2
P5_4/LCD1_DATA4
P5_6/LCD1_DATA6
0.1µF
P4_9
P2_13
P2_15
P5_1/LCD1_DATA1
P5_3/LCD1_DATA3
P5_4/LCD1_DATA4
P5_6/LCD1_DATA6
3VCC 5VCC
CP62
P4_9/LCD1_TCON4
P2_13/LCD1_DATA13
P2_15/LCD1_DATA15
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
J14
8611-060S
KEL
_18pF
P1_7
P1_6
P4_8
P5_0
P5_2
P5_9
P5_5
P5_7
P2_8
P2_10
J13
3VCC 5VCC
HIF3FC-40PA-2.54DSA
HRS
2
P5_1
4
P5_3
6
P5_4
8
P5_6
10
12
P2_9
14
P2_11
16
P2_12
18
P2_14
20
22
P5_10
24
P9_3
26
P9_4
28
P9_6
30
32
P4_14
34
P4_8
36
P4_9
38
P4_11
40
C12
P1_7/SDA3
P1_6/SCL3
P4_8/LCD1_TCON3
P5_0/LCD1_DATA0
P5_2/LCD1_DATA2
P5_9/LCD1_DATA16
P5_5/LCD1_DATA5
P5_7/LCD1_DATA7
P2_8/LCD1_DATA8
P2_10/LCD1_DATA10
CP58
P4_12
0.1µF
0.1µF
P4_12/LCD1_CLK
CP66
CP67
P4_14
P4_13
P4_15
_18pF
P4_14/LCD1_TCON1
P4_13/LCD1_TCON0
P4_15/LCD1_TCON2
C13
P2_8
P2_9
P2_10
P2_11
P2_12
P2_13
P2_14
P2_15
P5_9
P5_10
for R0P7724LE0011RL
5VCC 3VCC
5VCC 3VCC
_18pF
P5_6/LCD1_DATA6
P5_7/LCD1_DATA7
P2_8/LCD1_DATA8
P2_9/LCD1_DATA9
P2_10/LCD1_DATA10
P2_11/LCD1_DATA11
P2_12/LCD1_DATA12
P2_13/LCD1_DATA13
P2_14/LCD1_DATA14
P2_15/LCD1_DATA15
P5_9/LCD1_DATA16
P5_10/LCD1_DATA17
J12
XF2J-4024-12A
OMRON
3.3V
3.3V
3.3V
GND
GND
B0
B1
B2
B3
B4
B5
GND
G0
G1
G2
G3
G4
G5
R0
R1
R2
R3
R4
R5
GND
DE
HSYNC(NC)
VSYNC(NC)
GND
LCDCLK
GND
+5V
+5V
+5V
NC
SDA
SCL
INT
NC
RESET
C11
10kΩ
P5_0
P5_1
P5_2
P5_3
P5_4
P5_5
P5_6
P5_7
P5_0/LCD1_DATA0
P5_1/LCD1_DATA1
P5_2/LCD1_DATA2
P5_3/LCD1_DATA3
P5_4/LCD1_DATA4
P5_5/LCD1_DATA5
B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
R81
R80
_10kΩ
for LCD-KIT-B01
P1_7
SDA0
P1_7/SDA3
P4_11
TP_IRQ#
P4_11/LCD1_TCON6
A
A
CHANGE
Renesas Solutions Corp.
DRAWN
CHECKED
DESIGNED
APPROVED
RTK7721000B00000BR
LCD Output
( 5
/ 7
SCALE
DATE
5
4
D-RTK7721000B00000BR_C-A
13-07-02
3
2
1
)
5
4
3
2
1
[2,5,7] P10_[15:0]
[2,4,5,7]
P11_[15:0]
U8
ADV7123
Analog Devices
CLKOUT
CLK1
CLK2
CLK3
CLK4
GND
VDD
R125
18Ω
24
11
12
38
CTRL0
CTRL1
CTRL2
3VCC
TP5
10kΩ
10kΩ
TP6
R92
R93
TP7
TP8
75Ω
75Ω
75Ω
R87
0Ω
28
27
R88
0Ω
R89
R90
R91
G9
G8
G7
G6
G5
G4
G3
G2
G1
G0
AN3V
AN3V P11_14/LCD0_TCON0
P11_13/LCD0_TCON1
P11_14
P11_13
TP9
R94
1kΩ
36
37
R95
200Ω
D
FG 16
FG 17
1
AD1580
0.1µF
VREF
RSET
35
C14
0.1µF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R96
330Ω
3
2
D1
CP68
COMP
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
1
3
VR1
_PV37P501C01
AN3V
CLOCK
BLANK#
SYNC#
PSAVE#
VAA1
VAA2
VAA3
13
29
30
CP70
CP71
CP72
CP73
CP74
CP75
CP69
C15
4
0.1µF
6
8
3
2
5
7
IOB
IOB#
J15
XM4L-1542-132 (Tyco:1734530-1)
OMRON
R86
0Ω
32
31
25
26
REF
3VCC
R98
1
P11_15
_18pF
U9
CY2305SC-1H
Cypress
P11_15/LCD0_CLK
IOG
IOG#
34
33
2
_10kΩ
R97
_0Ω
23
22
21
20
19
18
17
16
15
14
P11_0
P11_1
P11_2
P11_3
P11_4
P11_5
P11_6
P11_7
P11_0/LCD0_DATA7
P11_1/LCD0_DATA6
P11_2/LCD0_DATA5
P11_3/LCD0_DATA4
P11_4/LCD0_DATA3
P11_5/LCD0_DATA2
P11_6/LCD0_DATA1
P11_7/LCD0_DATA0
3VCC
10
9
8
7
6
5
4
3
2
1
P10_8
P10_9
P10_10
P10_11
P10_12
P10_13
P10_14
P10_15
P10_8/LCD0_DATA15
P10_9/LCD0_DATA14
P10_10/LCD0_DATA13
P10_11/LCD0_DATA12
P10_12/LCD0_DATA11
P10_13/LCD0_DATA10
P10_14/LCD0_DATA9
P10_15/LCD0_DATA8
IOR
IOR#
0.1µF
0.01µF
0.1µF
0.01µF
0.1µF
0.01µF
D
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
GND1
GND2
48
47
46
45
44
43
42
41
40
39
P10_0
P10_1
P10_2
P10_3
P10_4
P10_5
P10_6
P10_7
P10_0/LCD0_DATA23
P10_1/LCD0_DATA22
P10_2/LCD0_DATA21
P10_3/LCD0_DATA20
P10_4/LCD0_DATA19
P10_5/LCD0_DATA18
P10_6/LCD0_DATA17
P10_7/LCD0_DATA16
C
C
[2,4,5] P4_[15:0]
[2,5] P9_[7:2]
U10
ADV7123
Analog Devices
R126
18Ω
24
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
R112
R113
R114
R115
R116
R117
R123
R124
16
15
14
13
12
11
10
9
VREF
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
RSET
35
C16
0.1µF
AN3V P4_10/LCD1_TCON5
P4_14/LCD1_TCON1
TP11
P4_10
P4_14
R108
200Ω
TP12
TP13
TP14
R107
1kΩ
36
37
TP10
10kΩ
10kΩ
R101
0Ω
AN3V
COMP
3VCC
75Ω
75Ω
75Ω
R100
0Ω
28
27
R105
R106
G9
G8
G7
G6
G5
G4
G3
G2
G1
G0
32
31
R109
330Ω
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FG 16
FG 17
14 : Hsync
15 : Vsync
B
3
1
3
VR2
_PV37P501C01
AN3V
CLOCK
BLANK#
SYNC#
PSAVE#
VAA1
VAA2
VAA3
13
29
30
25
26
3VCC
SW14
A6S-8104
OMRON
1
2
3
4
5
6
7
8
11
12
38
CTRL3
CTRL4
CTRL5
IOB
IOB#
J16
XM4L-1542-132 (Tyco:1734530-1)
OMRON
R99
0Ω
1
AD1580
0.1µF
23
22
21
20
19
18
17
16
15
14
IOG
IOG#
34
33
R102
R103
R104
P5_7
P5_6
P5_5
P5_4
P5_3
P5_2
P5_1
P5_0
C17
VDD
8
3
2
5
7
CP77
0.1µF
6
CLKOUT
CLK1
CLK2
CLK3
CLK4
GND
REF
3VCC
4
1
P4_12
P5_7/LCD1_DATA7
P5_6/LCD1_DATA6
P5_5/LCD1_DATA5
P5_4/LCD1_DATA4
P5_3/LCD1_DATA3
P5_2/LCD1_DATA2
P5_1/LCD1_DATA1
P5_0/LCD1_DATA0
_18pF
U11
CY2305SC-1H
Cypress
P4_12/LCD1_CLK
10
9
8
7
6
5
4
3
2
1
R111
R110
_0Ω
P2_15
P2_14
P2_13
P2_12
P2_11
P2_10
P2_9
P2_8
IOR
IOR#
2
D2
CP76
_10kΩ
B
P2_15/LCD1_DATA15
P2_14/LCD1_DATA14
P2_13/LCD1_DATA13
P2_12/LCD1_DATA12
P2_11/LCD1_DATA11
P2_10/LCD1_DATA10
P2_9/LCD1_DATA9
P2_8/LCD1_DATA8
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
2
3VCC
48
47
46
45
44
43
42
41
40
39
P9_7
P9_6
P9_5
P9_4
P9_3
P9_2
P5_10
P5_9
P9_7/LCD1_DATA23
P9_6/LCD1_DATA22
P9_5/LCD1_DATA21
P9_4/LCD1_DATA20
P9_3/LCD1_DATA19
P9_2/LCD1_DATA18
P5_10/LCD1_DATA17
P5_9/LCD1_DATA16
CTRL[5:0]
0.1µF
0.01µF
0.1µF
0.01µF
0.1µF
0.01µF
P2_[15:0]
CP78
CP79
CP80
CP81
CP82
CP83
P5_[10:0]
[2,3,4,5]
GND1
GND2
[2,3,5,7]
CTRL0
CTRL1
CTRL2
CTRL3
CTRL4
CTRL5
SW14-7 [3]
TP15
ON:Low, OFF:Hi
A
A
CHANGE
Renesas Solutions Corp.
DRAWN
CHECKED
DESIGNED
APPROVED
RTK7721000B00000BR
Video Encoder
( 6
/ 7
SCALE
DATE
5
4
D-RTK7721000B00000BR_C-A
13-07-02
3
2
1
)
1
2
3
4
P10_[15:0]
[2,5,6] P10_[15:0]
[2,4,5,6]
P11_[15:0]
P11_[15:0]
3VCC
DV ch0
3VCC
CMOS Camera
R119
3VCC
2
1
RES# [2,4]
P11_1/DV0_DATA13
P11_3/DV0_DATA15
P11_4/DV0_DATA16
P11_6/DV0_DATA18
P11_1
P11_3
P11_4
P11_6
P11_9/DV0_DATA21
P11_11/DV0_DATA23
P11_9
P11_11
P10_1/DV0_VSYNC
P10_1
X2
SG-8002CA_27MHz
3
VCC OUT
GND OE
P10_5
P10_7
P10_8
P10_10
P10_5/DV0_DATA1
P10_7/DV0_DATA3
P10_8/DV0_DATA4
P10_10/DV0_DATA6
P10_13
P10_15
P11_0
P11_2
P10_13/DV0_DATA9
P10_15/DV0_DATA11
P11_0/DV0_DATA12
P11_2/DV0_DATA14
P11_5
P11_7
P11_8
P11_10
P11_5/DV0_DATA17
P11_7/DV0_DATA19
P11_8/DV0_DATA20
P11_10/DV0_DATA22
P10_0
P10_2
P10_0/DV0_CLK
P10_2/DV0_HSYNC
A
1
CP88
0.1µF
4
P1_1/SDA0
JP4
HWP-3P-G_23
R121
CP84
0.1µF
18Ω
2
P1_1
P10_3/RST_Ctrl
P10_9
P10_11
P10_12
P10_14
J18
5VCC
HIF3FC-40PA-2.54DSA
HRS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
R120
34
18Ω
36
38
40
0.1µF
P1_0
P10_0
P10_3
P10_9/DV0_DATA5
P10_11/DV0_DATA7
P10_12/DV0_DATA8
P10_14/DV0_DATA10
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
CP87
P10_1
P1_0/SCL0
P10_0/VIO_CLK
P10_7/VIO_D3
P10_9/VIO_D5
P10_11/VIO_D7
P10_13/VIO_D9
P10_5/VIO_D1
P10_4
P10_6
0.1µF
P10_1/VIO_VD
3
P10_7
P10_9
P10_11
P10_13
P10_5
P10_4/DV0_DATA0
P10_6/DV0_DATA2
CP86
P10_2
R118
22kΩ
P10_2/VIO_HD
1
3
5
7
9
11
13
15
17
19
21
23
25
18Ω
P10_6
P10_8
P10_10
P10_12
P10_4
5VCC
0.1µF
P10_6/VIO_D2
P10_8/VIO_D4
P10_10/VIO_D6
P10_12/VIO_D8
P10_4/VIO_D0
J17
N2526-6002RB
3M
2
4
6
8
10
12
14
16
18
20
22
24
26
CP85
5VCC
A
5
B
[2,3,5,6]
B
P5_[10:0]
P1_[15:0]
[2,4,5] P1_[15:0]
DV ch1
5VCC 3VCC
P5_0/DV1_DATA0
P5_2/DV1_DATA2
P5_0
P5_2
P5_4/DV1_DATA4
P5_6/DV1_DATA6
P5_4
P5_6
0.1µF
0.1µF
0.1µF
0.1µF
CP91
CP92
R122
18Ω
CP90
P1_5
3VCC 5VCC
J19
HIF3FC-20PA-2.54DSA
HRS
2
P5_1
4
P5_3
6
8
P5_5
10
P5_7
12
14
P1_6
16
P1_7
18
20
CP89
P1_5/DV1_CLK
1
3
5
7
9
11
13
15
17
19
P5_1/DV1_DATA1
P5_3/DV1_DATA3
P5_5/DV1_DATA5
P5_7/DV1_DATA7
P1_6/DV1_VSYNC
P1_7/DV1_HSYNC
C
C
D
D
CHANGE
Renesas Solutions Corp.
DRAWN
CHECKED
DESIGNED
APPROVED
RTK7721000B00000BR
CMOS, DV
( 7
/ 7
SCALE
DATE
1
2
D-RTK7721000B00000BR_C-A
13-07-02
3
4
5
)
REVISION
HISTORY
Rev.
R7S72100 CPU optional board RTK7721000B00000BR User's Manual
Issue date
Description
Page
Summary
0.01
Nov. 5, 2012.
-
Preliminary issued
0.02
Nov. 12, 2012
-
Review specifications
0.03
Nov. 16, 2012
-
Correct errors in expansion connectors in the table of pin function
0.04
Jul. 12, 2013
-
Add chappter 1, 3, and cover
Correct errors found when deciding details.
Check and review the pin names
Add general name for the board (GENMAI)
Correct errors
0.05
Sep. 06, 2013
-
Correct errors
R7S72100 CPU optional board RTK7721000B00000BR
User's Manual
Publication Date: Sep. 06, 2013 Rev.0.05
Published by: Renesas Electronics Corporation
http://www.renesas.com
SALES OFFICES
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-651-700, Fax: +44-1628-651-804
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
© 2013 Renesas Electronics Corporation. All rights reserved.
Colophon 1.3
16
R7S72100 CPU (GENMAI) Optional Board
RTK7721000B00000BR
User's Manual
R20UT2696EJ0005