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S3C2500B
ETHERNET CONTROLLER
7.4.1.9 BDMA/MAC Receive Interrupt Enable Register
Table 7-20. BMRXINTEN Register
Registers
Address
R/W
Description
Reset Value
BMRXINTENA
0xF00A001C
R/W
BDMA/MAC Rx Interrupt Enable Register
0x00000000
BMRXINTENB
0xF00C001C
R/W
BDMA/MAC Rx Interrupt Enable Register
0x00000000
Table 7-21. BDMA/MAC Receive Interrupt Enable Register Description
Bit Number
Bit Name
Description
[0]
Enable MAC Rx missed roll
(MissRollIE)
This bit enables MissRoll interrupt.
[1]
Enable MAC Rx alignment
(AlignErrIE)
This bit enables AlignErr interrupt
[2]
Enable MAC Rx CRC error
(CRCErrIE)
This bit enables CRCErr interrupt.
[3]
Enable MAC Rx overflow
(OverflowIE)
This bit enables Overflow interrupt.
[4]
Enable MAC Rx long error
(LongErrIE)
This bit enables LongErr interrupt.
[5]
Enable MAC Rx receive parity This bit enables RxParErr interrupt.
(RxParErrIE)
[6]
[15:7]
–
Factorial test bit
Reserved
Not applicable.
[16]
Enable BDMA Rx done for
every received frames
(BRxDoneIE)
This bit enables BRxDone interrupt.
[17]
Enable BDMA Rx not owner
interrupt (BRxNOIE)
This bit enables BRxNO interrupt.
[18]
Enable BDMA Rx maximum
size over interrupt
(BRxMSOIE)
This bit enables BRxMSO interrupt.
[19]
Enable BDMA Rx
buffer(BRxBUFF) Overflow
Interrupt(BRxFullIE)
This bit enables BRxFull interrupt.
[20]
Enable BDMA Rx early
notification interrupt
(BRxEarlyIE)
This bit enables BRxEarly interrupt.
Reserved
Not applicable.
[31:21]
7-21