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General Purpose Timer Module (GPT) 20.8 Reset Reset initializes the GPT registers to a known startup state as described in Section 20.6, “Memory Map and Registers.” 20.9 Interrupts Table 20-24 lists the interrupt requests generated by the timer. Table 20-24. GPT Interrupt Requests Interrupt Request Flag Enable Bit Channel 3 IC/OC C3F C3I Channel 2 IC/OC C2F C2I Channel 1 IC/OC C1F C1I Channel 0 IC/OC C0F C0I PAOVF PAOVI PA input PAIF PAI Timer overflow TOF TOI PA overflow 20.9.1 GPT Channel Interrupts (CnF) A channel flag is set when an input capture or output compare event occurs. Clear a channel flag by writing a 1 to it. NOTE When the fast flag clear all bit (GPTSCR1[TFFCA]) is set, an input capture read or an output compare write clears the corresponding channel flag. When a channel flag is set, it does not inhibit subsequent output compares or input captures 20.9.2 Pulse Accumulator Overflow (PAOVF) PAOVF is set when the 16-bit pulse accumulator rolls over from 0xFFFF to 0x0000. If the PAOVI bit in GPTPACTL is also set, PAOVF generates an interrupt request. Clear PAOVF by writing a 1 to this flag. NOTE When the fast flag clear all enable bit (GPTSCR1[TFFCA]) is set, any access to the pulse accumulator counter registers clears all the flags in GPTPAFLG. 20.9.3 Pulse Accumulator Input (PAIF) PAIF is set when the selected edge is detected at the PAI pin. In event counter mode, the event edge sets PAIF. In gated time accumulation mode, the trailing edge of the gate signal at the PAI pin sets PAIF. If the MCF52223 ColdFire® Integrated Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor 20-21
