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Debug Module
DRc[4:0]: 0x09 (PBMR)
Access: Supervisor write-only
BDM write-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R
W
Mask
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Figure 27-8. PC Breakpoint Mask Register (PBMR)
Table 27-11. PBMR Field Descriptions
Field
31–0
Mask
27.3.7
Description
PC Breakpoint Mask.
0 The corresponding PBR0 bit is compared to the appropriate PC bit.
1 The corresponding PBR0 bit is ignored.
Address Breakpoint Registers (ABLR, ABHR)
The ABLR and ABHR define regions in the processor’s data address space that can act as part of the
trigger. These register values are compared with the address for each transfer on the processor’s high-speed
local bus. The trigger definition register (TDR) identifies the trigger as one of three cases:
• Identically the value in ABLR
• Inside the range bound by ABLR and ABHR inclusive
• Outside that same range
ABLR and ABHR are accessible in supervisor mode using the WDEBUG instruction and via the BDM
port using the WDMREG command.
DRc[4:0]: 0x0C (ABHR)
0x0D (ABLR)
Access: Supervisor write-only
BDM write-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R
W
Address
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Figure 27-9. Address Breakpoint Registers (ABLR, ABHR,)
Table 27-12. ABLR Field Description
Field
Description
31–0
Low Address. Holds the 32-bit address marking the lower bound of the address breakpoint range. Breakpoints for
Address specific single addresses are programmed into ABLR.
Table 27-13. ABHR Field Description
Field
Description
31–0
High Address. Holds the 32-bit address marking the upper bound of the address breakpoint range.
Address
MCF52223 ColdFire® Integrated Microcontroller Reference Manual, Rev. 4
Freescale Semiconductor
27-15