Download User Manual ST10F272

UM0381
System programming
The EXTS (extend segment) instruction allows switching to a 64 Kbyte segment oriented
data access scheme for 1...4 instructions without having to change the current DPPs. In this
case all 16 bits of the operand address are used as segment offset, with the segment taken
from the EXTS instruction. This greatly simplifies address calculation with continuous data
like huge arrays in “C”.
EXAMPLE:
Note:
#15, #1
; The override seg. is #15
(0F’0000h...0F’FFFFh)
MOV
R0, [R14]
; The (16 Bit) segment offset is stored in R14
MOV
R1, [R13]
; This instruction uses the standard DPP
scheme!
EXTS
Instructions EXTP and EXTS inhibit interrupts the same way as ATOMIC.
Short addressing in the extended SFR (ESFR) space
The short addressing modes of the ST10F272 (REG or bitOFF) implicitly access the SFR
space. The additional ESFR space would have to be accessed via long addressing modes
(MEM or [Rw]).
The EXTR (extend register) instruction redirects accesses in short addressing modes to the
ESFR space for 1...4 instructions, so the additional registers can be accessed this way, too.
The EXTPR and EXTSR instructions combine the DPP override mechanism with the
redirection to the ESFR space using a single instruction.
Note:
Instructions EXTR, EXTPR and EXTSR inhibit interrupts the same way as ATOMIC.
The switching to the ESFR area and data page overriding is checked by the development
tools or handled automatically.
Nested locked sequences
Each of the described extension instruction and the ATOMIC instruction starts an internal
“extension counter” counting the effected instructions. When another extension or ATOMIC
instruction is contained in the current locked sequence this counter is restarted with the
value of the new instruction. This allows the construction of locked sequences longer than 4
instructions.
Note:
Interrupt latencies may be increased when using locked code sequences.
PEC requests are not serviced during idle mode, if the IDLE instruction is part of a locked
sequence.
27.10
Handling the internal Flash
The ST10F272 provides and controls up to 256 Kbytes of internal on-chip IFlash memory
that may store code as well as data. Access to this internal Flash area is controlled during
the reset configuration and via software.
Configuration during reset
The default memory configuration of the ST10F272 Memory is determined by the state of
the EA pin at reset. This value is stored in the Internal ROM Enable bit (named ROMEN) of
the SYSCON register.
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