Download User Manual ST10F272

System reset
UM0381
with P0L.1 high.
Default: Adapt Mode is off.
Note:
When XTAL1 is fed by an external clock generator (while XTAL2 is left open), this clock
signal may also be used to drive the emulator device.
However, if a crystal is used, the emulator device’s oscillator can use this crystal only, if at
least XTAL2 of the original device is disconnected from the circuitry (the output XTAL2 will
still be active in Adapt Mode).
Reserved: P0L.2 - P0L.3
These pins must be always left open (or driven high) during reset, to avoid ST10 enters
particular test mode and consequently does not work properly.
Default: Test Modes are off.
Bootstrap loader mode: P0L.4 - P0L.5
Pins P0L.4 and P0L.5 (BSL) activate the on-chip bootstrap loader modes. The bootstrap
loader allows moving the start code into the IRAM of the ST10F272 via the serial interface
ASC0 or CAN1. The MCU will remain in bootstrap loader mode until a hardware reset with
P0L.4 and P0L.5 both high or a software reset occurrence. Refer to Section 15: The
bootstrap loader on page 295 for details.
Default: The ST10F272 starts fetching code from location 00’0000h, the bootstrap loader is
off.
External bus type: P0L.6 - P0L.7
Pins P0L.7 and P0L.6 (BUSTYP) select the external bus type during reset, if an external
start is selected via pin EA. This allows the configuration of the external bus interface of the
ST10F272 even for the first code fetch after reset. The two bits are copied into bit-field BTYP
of register BUSCON0. P0L.7 controls the data bus width, while P0L.6 controls the address
output (multiplexed or de-multiplexed). This bit-field may be changed via software after
reset, if required.
BTYP encoding
External data bus width
External address bus mode
00
8-bit Data
De-multiplexed Addresses
01
8-bit Data
Multiplexed Addresses
10
16-bit Data
De-multiplexed Addresses
11
16-bit Data
Multiplexed Addresses
PORT0 and PORT1 are automatically switched to the selected bus mode. In multiplexed bus
modes PORT0 drives both the 16-bit intra-segment address and the output data, while
PORT1 remains in high impedance state as long as no de-multiplexed bus is selected via
one of the BUSCON registers. In de-multiplexed bus modes PORT1 drives the 16-bit intrasegment address, while PORT0 or P0L (according to the selected data bus width) drives the
output data.
For a 16-bit data bus BHE is automatically enabled, for an 8-bit data bus BHE is disabled via
bit BYTDIS in register SYSCON.
Default: 16-bit data bus with multiplexed addresses.
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