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UM0381 System reset Figure 192. Asynchronous power-on RESET (EA = 0) ≥ 1.2ms (for resonator oscillation + PLL stabilization) ≥ 10.2ms (for crystal oscillation + PLL stabilization) ≥ 1ms (for on-chip VREG stabilization) VDD 3..8 TCL1) V18 XTAL1 ... RPD RSTIN ≥ 50ns ≤ 500ns RSTF (After Filter) 3..4 TCL P0[15:13] transparent not t. P0[12:2] transparent not t. P0[1:0] not transparent not t. 8 TCL ALE RST Latching point of Port0 for system start-up configuration Note 1. 3 to 8 TCL depending on clock source selection. Hardware reset The asynchronous reset must be used to recover from catastrophic situations of the application. It may be triggered by the hardware of the application. Internal hardware logic and application circuitry are described in Section 23.7: Reset circuitry on page 463 and Figure 204, Figure 205 and Figure 207. It occurs when RSTIN is low and RPD is detected (or becomes) low as well. 449/537
