Download A10 User manual V1.50 - linux

Allwinner Technology CO., Ltd.
A10
For 16-bits received audio sample:
Mode 0: RXDATA[31:0] = {FIFO_O[23:8], 16’h0}
Mode 1: RXDATA[31:0] = {16{FIFO_O[23]},
FIFO_O[23:8]}
23:13
12:8
7
/
R/W
R/W
/
0xF
RX_FIFO_TRG_LEVEL.
RX FIFO Trigger Level (RXTL[4:0])
Interrupt and DMA request trigger level for TX FIFO
normal condition
IRQ/DRQ Generated when WLEVEL ＞ RXTL[4:0]
Notes:
1. WLEVEL represents the number of valid samples in
the RX FIFO
0x0
ADC_MONO_EN.
ADC Mono Enable.
0: Stereo, 16 levels FIFO
1: mono, 32 levels FIFO
When set to ‘1’, Only left channel samples are recorded
RX_SAMPLE_BITS.
Receiving Audio Sample Resolution
0: 16 bits
1: 24 bits
6
R/W
0x0
5
/
/
4
R/W
0x0
ADC_IRQ_EN.
ADC FIFO Data Available IRQ Enable.
0: Disable
1: Enable
R/W
0x0
2
/
/
0
R/W
R/W
/
ADC_DRQ_EN.
ADC FIFO Data Available DRQ Enable.
0: Disable
1: Enable
3
1
/
/
0x0
ADC_OVERRUN_IRQ_EN.
ADC FIFO Over Run IRQ Enable
0: Disable
1: Enable
0x0
ADC_FIFO_FLUSH.
ADC FIFO Flush.
Write ‘1’ to flush TX FIFO, self clear to ‘0’.
A10 User Manual V1.50
Copyright © 2013 Allwinner Technology. All Rights Reserved.
2013/8/20
260