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EFM8UB2 Reference Manual
Universal Asynchronous Receiver/Transmitter 1 (UART1)
21.4 UART1 Control Registers
21.4.1 SCON1: UART1 Serial Port Control
Bit
7
6
5
4
3
2
1
0
Name
OVR
PERR
Reserved
REN
TBX
RBX
TI
RI
Access
RW
RW
R
RW
RW
R
RW
R
0
0
Varies
0
0
0
0
0
Reset
SFR Page = ALL; SFR Address: 0xD2
Bit
Name
Reset
Access
Description
7
OVR
0
RW
Receive FIFO Overrun Flag.
This bit indicates a receive FIFO overrun condition, where an incoming character is discarded due to a full FIFO. This bit
must be cleared by firmware.
6
Value
Name
Description
0
NOT_SET
Receive FIFO overrun has not occurred.
1
SET
Receive FIFO overrun has occurred.
PERR
0
RW
Parity Error Flag.
When parity is enabled, this bit indicates that a parity error has occurred. It is set to 1 when the parity of the oldest byte in
the FIFO (available when reading SBUF1) does not match the selected parity type. This bit must be cleared by firmware.
Value
Name
Description
0
NOT_SET
Parity error has not occurred.
1
SET
Parity error has occurred.
5
Reserved
Must write reset value.
4
REN
0
RW
Receive Enable.
This bit enables/disables the UART receiver. When disabled, bytes can still be read from the receive FIFO, but the receiver
will not place new data into the FIFO.
3
Value
Name
Description
0
RECEIVE_DISABLED
UART1 reception disabled.
1
RECEIVE_ENABLED
UART1 reception enabled.
TBX
0
Extra Transmission Bit.
RW
The logic level of this bit will be assigned to the extra transmission bit when XBE = 1 in the SMOD1 register. This bit is not
used when parity is enabled.
2
RBX
0
R
Extra Receive Bit.
RBX is assigned the value of the extra bit when XBE = 1 in the SMOD1 register. This bit is not valid when parity is enabled
or when XBE is cleared to 0.
1
TI
0
RW
Transmit Interrupt Flag.
Set to a 1 by hardware after data has been transmitted at the beginning of the STOP bit. When the UART1 TI interrupt is
enabled, setting this bit causes the CPU to vector to the UART1 interrupt service routine. This bit must be cleared by firmware.
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