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
RTY_I: Retry input indicates that interface is not ready to operate and
cycle must be retried.

SEL_O(): Select output array is used to indicate where valid data is
expected on DAT_I().

STB_O: Strobe output indicates a valid data transfer cycle.

TGA_O(): Address tag type; provides extra information associated with
ADR_O().

TGC_O(): Cycle tag type provides extra information associated with bus
cycle.

WE_O(): Write enable output; indicates if current cycle is read or write.
2.3.2 Wishbone Operation
The Wishbone bus has multiple operating modes. The present assignment will
focus on the standard single read cycle (Figure 2-8) and write cycle (Figure
2-9). It is also important to consider that the data sent or received at this time is
the same width as the bus itself (16 Bits). Both read and write will be explained
using the relevant signals for the project [8].
2.3.2.1 Single Read Cycle
The following description is a summary of the information found on the
OpenCores Wishbone manual. It explains how the read cycle works on a
Wishbone interface. The explanation is separated by clock cycles for practical
purposes. Figure 2-8 represents this bus transaction as well.
Clock Edge 0

Master presents valid address on ADR_O.

Master negates WE_O to indicate read cycle.

Master asserts CYC_O to indicate the start of cycle.

Master asserts STB_O to indicate the start of phase.
Clock Edge 1
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