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files will be used to generate the documentation PDF and, more importantly,
multiple snippets of Python code. These small pieces of code then will be
united to form the design template.
Ideally, the design template will be the base to generate two sets of files: the
Verilog files for the RTL design and the Arch C files for implementing the
assembler language used by the design, represented by section B on Figure
2-10.
The design flow will also be in charge of installing the compilation tools for
Verilog and Arch C if needed; finally the design flow will do the simulation of the
previously generated Verilog file. The design flow is not the main focus of this
assignment and is still a work in progress. Therefore, changes were applied
continuously during the development of the assignment. The assignment
focused on section B of the design flow, creating the RTL Files and the Arch C
files.
2.4.1 Arch C
A brief introduction taken from the Arch C User Manual [9] will be given to
provide an overall understanding of the process taking place when generating
the stack processor assembler language.
The solution to simplify the development and testing of a design in recent years
has been the use of Architecture Description Languages (ADL). Due to the
increasing complexity of modern designs and time-to-market restraints,
designers are moving from hardware description languages to system level
designs, where
automatic generation of a software toolkit (composed by
assemblers, linkers, compiler and simulators ) is mandatory [10] [11] [9].
Arch C is a language that follows the System C syntax style and is capable of
describing a processor’s architecture and a memory hierarchy. The goal of
Arch C is to provide information at the right abstraction level to provide
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