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Download UM10850 LPC5410x User manual
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UM10850 NXP Semiconductors Chapter 31: LPC5410x Flash API Up to 4 parameters can be passed in the r0, r1, r2 and r3 registers respectively (see the ARM Thumb Procedure Call Standard SWS ESPC 0002 A-05). Additional parameters are passed on the stack. Up to 4 parameters can be returned in the r0, r1, r2 and r3 registers respectively. Additional parameters are returned indirectly via memory. Some of the IAP calls require more than 4 parameters. If the ARM suggested scheme is used for the parameter passing/returning then it might create problems due to difference in the C compiler implementation from different vendors. The suggested parameter passing scheme reduces such risk. The flash memory is not accessible during a write or erase operation. IAP commands, which results in a flash write/erase operation, use 32 bytes of space in the top portion of the on-chip RAM for execution. The user program should not be use this space if IAP flash programming is permitted in the application. Table 478. IAP Command Summary IAP Command Command code Reference Prepare sector(s) for write operation 50 (decimal) Table 479 Copy RAM to flash 51 (decimal) Table 480 Erase sector(s) 52 (decimal) Table 481 Blank check sector(s) 53 (decimal) Table 482 Read Part ID 54 (decimal) Table 483 Read Boot code version 55 (decimal) Table 484 Compare 56 (decimal) Table 485 Reinvoke ISP 57 (decimal) Table 486 Read UID 58 (decimal) Table 487 Erase page(s) 59 (decimal) Table 488 Read Signature 70 (decimal) Table 489 &RPPDQG3DUDPHWHU$UUD\ FRPPDQGBSDUDP>@ &RPPDQGFRGH FRPPDQGBSDUDP>@ 3DUDP FRPPDQGBSDUDP>@ 3DUDP FRPPDQGBSDUDP>Q@ 3DUDPQ $505(*,67(5U $505(*,67(5U 6WDWXV5HVXOW$UUD\ VWDWXVBUHVXOW>@ 6WDWXVFRGH VWDWXVBUHVXOW>@ 5HVXOW VWDWXVBUHVXOW>@ 5HVXOW VWDWXVBUHVXOW>Q@ 5HVXOWQ Fig 56. IAP parameter passing UM10850 User manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 5 November 2014 © NXP B.V. 2014. All rights reserved. 409 of 437
