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UM10850
NXP Semiconductors
Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2)
– as a slave transmitter, after each after each data byte is sent and the matching
acknowledge is received from the master
In each case, the relevant pending flag (MSTPENDING or SLVPENDING) is set at the
point where clock stretching occurs.
23.7.2 Time-out
A time-out feature on an I2C interface can be used to detect a “stuck” bus and potentially
do something to alleviate the condition. Two different types of time-out are supported.
Both types apply whenever the I2C block and the time-out function are both enabled.
Master, Slave, or Monitor functions do not need to be enabled.
In the first type of time-out, reflected by the EVENTTIMEOUT flag in the STAT register,
the time between bus events governs the time-out check. These events include Start,
Stop, and all changes on the I2C clock (SCL). This time-out is asserted when the time
between any of these events is longer than the time configured in the TIMEOUT register.
This time-out could be useful in monitoring an I2C bus within a system as part of a method
to keep the bus running of problems occur.
The second type of I2C time-out is reflected by the SCLTIMEOUT flag in the STAT
register. This time-out is asserted when the SCL signal remains low longer than the time
configured in the TIMEOUT register. This corresponds to SMBus time-out parameter
TTIMEOUT. In this situation, a slave could reset its own I2C interface in case it is the
offending device. If all listening slaves (including masters that can be addressed as
slaves) do this, then the bus will be released unless it is a current master causing the
problem. Refer to the SMBus specification for more details.
Both types of time-out are generated only when the I2C bus is considered busy, i.e. when
there has been a Start condition more recently than a Stop condition.
23.7.3 Ten-bit addressing
Ten-bit addressing is accomplished by the I2C master sending a second address byte to
extend a particular range of standard 7-bit addresses. In the case of the master writing to
the slave, the I2C frame simply continues with data after the 2 address bytes. For the
master to read from a slave, it needs to reverse the data direction after the second
address byte. This is done by sending a Repeated Start, followed by a repeat of the same
standard 7-bit address, with a Read bit. The slave must remember that it had been
addressed by the previous write operation and stay selected for the subsequent read with
the correct partial I2C address.
For the Master function, the I2C is simply instructed to perform the 2-byte addressing as a
normal write operation, followed either by more write data, or by a Repeated Start with a
repeat of the first part of the 10-bit slave address and then reading in the normal fashion.
For the Slave function, the first part of the address is automatically matched in the same
fashion as 7-bit addressing. The Slave address qualifier feature (see Section 23.6.14) can
be used to intercept all potential 10-bit addresses (first address byte values F0 through
F6), or just one. In the case of Slave Receiver mode, data is received in the normal
fashion after software matches the first data byte to the remaining portion of the 10-bit
address. The Slave function should record the fact that it has been addressed, in case
there is a follow-up read operation.
UM10850
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 5 November 2014
© NXP B.V. 2014. All rights reserved.
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