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UM10850
NXP Semiconductors
Chapter 24: LPC5410x System FIFO for Serial Peripherals
For instance, if TimeoutBase is set to 5, then 4 bits of the timeout timer starting at bit 5 are
compared to TimeoutValue. Since bit 5 changes every 32 counts of the timeout timer, the
maximum time for a timeout to occur (since the timer may change immediately after data
is entered into the FIFO) is TimeoutValue (a range of 2 to 15) * 32 clocks. The source of
the timeout clock is device dependent.
24.5.8 Status register for USARTn
The STATUSART register provides information about the current state of the USART
FIFOs. Each USART has a dedicated STATUSART register.
Table 384. Address map STATUSART[0:3] registers
Peripheral
Base address
Offset
Increment
Dimension
VFIFO
0x1C03 8000
[0x1004:0x1304]
0x100
4
Table 385. Status register for USARTn (STATUSART[0:3], address offset [0x1004:0x1304]) bit description
Bit
Symbol
Description
Reset Value
0
RXTH
Receive FIFO Threshold. When 1, the receive FIFO threshold has been reached. This is
a read-only bit.
0
1
TXTH
Transmit FIFO Threshold. When 1, the transmit FIFO threshold has been reached. This
is a read-only bit.
0
3:2
-
Reserved. Read value is undefined, only zero should be written.
4
RX
TIMEOUT
Receive FIFO Timeout. When 1, the receive FIFO has timed out, based on the timeout
configuration in the CFGUSART register. The timeout condition can be cleared by
writing a 1 to this bit, by enabling or disabling the timeout interrupt, or by writing a 1 to
the timeout interrupt enable.
6:5
-
Reserved. Read value is undefined, only zero should be written.
7
BUSERR
Bus Error. When 1, a bus error has occurred while processing data for USARTn. The
bus error flag can be cleared by writing a 1 to this bit.
0
8
RXEMPTY
Receive FIFO Empty. When 1, the receive FIFO is currently empty. This is a read-only
bit.
1
9
TXEMPTY
Transmit FIFO Empty. When 1, the transmit FIFO is currently empty. This is a read-only
bit.
1
NA
0
NA
15:10 -
Reserved. Read value is undefined, only zero should be written.
23:16 RXCOUNT
Receive FIFO Count. Indicates how many entries may be read from the receive FIFO. 0
= FIFO empty. This is a read-only field.
0
31:24 TXCOUNT
Transmit FIFO Count. Indicates how many entries may be written to the transmit FIFO. 0
= FIFO full. This is a read-only field that is valid only when the TxFIFO is fully configured
and enabled.
0
UM10850
User manual
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Rev. 1.0 — 5 November 2014
NA
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