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UM10850
NXP Semiconductors
Chapter 13: LPC5410x SCTimer/PWM (SCT0)
13.6.19 SCT match registers 0 to 12 (REGMODEn bit = 0)
Match registers are compared to the counters to help create events. When the UNIFY bit
is 0, the L and H registers are independently compared to the L and H counters. When
UNIFY is 1, the L and H registers hold a 32-bit value that is compared to the unified
counter. A Match can only occur in a clock in which the counter is running (STOP and
HALT are both 0).
Match registers can be read at any time. Writing to the MATCH_L, MATCH_H, or unified
register is only allowed when the corresponding counter is halted (HALT bits are set to 1 in
the CTRL register). Match events occur in the SCT clock in which the counter is (or would
be) incremented to the next value. When a Match event limits its counter as described in
Section 13.6.3, the value in the Match register is the last value of the counter before it is
cleared to zero (or decremented if BIDIR is 1).
There is no “write-through” from Reload registers to Match registers. Before starting a
counter, software can write one value to the Match register used in the first cycle of the
counter and a different value to the corresponding Match Reload register used in the
second cycle.
Table 222. Address map MATCH[0:12] registers
Peripheral
Base address
Offset
Increment
Dimension
SCT0
0x1C01 8000
[0x100:0x130]
0x4
13
Table 223. SCT match registers 0 to 12 (MATCH[0:12], address offsets [0x100:0x130]) bit description (REGMODEn
bit = 0)
Bit
Symbol
Description
Reset value
15:0
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When 0
UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the
unified counter.
31:16 MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When 0
UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the
unified counter.
13.6.20 SCT capture registers 0 to 12 (REGMODEn bit = 1)
These registers allow software to read the counter values at which the event selected by
the corresponding Capture Control registers occurred.
Table 224. Address map CAP[0:12] registers
Peripheral
Base address
Offset
Increment
Dimension
SCT0
0x1C01 8000
[0x100:0x130]
0x4
13
Table 225. SCT capture registers 0 to 12 (CAP[0:12], address offsets [0x100:0x130]) bit description (REGMODEn bit
= 1)
Bit
Symbol
Description
Reset value
15:0
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured.
When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last
captured.
0
31:16 CAPn_H
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When UNIFY = 0, read the 16-bit counter value at which this register was last captured.
0
When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last
captured.
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Rev. 1.0 — 5 November 2014
© NXP B.V. 2014. All rights reserved.
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