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UM10208
Chapter 5: LPC288x Processor cache and memory mapping
Rev. 01 — 5 September 2006
User manual
1. Introduction
The ARM CPU in the LPC288x has been extended with a 2-way set-associative cache
controller. The cache is 8 kB in size and can store both data and instruction code.
The biggest benefit of this cache is that if code is run from non-zero-wait state memory, for
instance the internal FLASH controller, these memories can still behave almost as if they
are zero-wait state memory. If code is executed from the cache, the CPU will run at 1
clock per instruction most of the time.
The trade-off in introducing this cache is that each AHB access that bypasses the cache
will have an extra wait state inserted. So, it is generally advisable that both instruction
caching and data caching are turned on for most regions of on and off-chip memory.
2. Features
• 8 kB in a 2-way set-associative cache
• Configured as 2×128 cache lines of eight 32-bit words each
• Sixteen pages of address mapping each allow any address range to be selected for
caching
3. Cache definitions
• A 2-way cache includes two cache lines that can be used for each memory address.
• A cache line is 8 consecutive 32 bit words. The cache contains 128 cache lines, each
with 2 ways, making 8 kB total.
• The association of memory addresses to cache lines is that cache line 0 corresponds
with address word addresses 0x0 to 0x07, cache line 1 corresponds with word
addresses 0x08 to 0x0F, etc. After 1024 words, this repeats. Thus, word address 0,
word address 1024, word address 2048, ... all map to cache line 0.
• A tag word is associated with each cache line. The tag includes the address each
cache line is currently associated with, a "dirty" flag that indicates if the line has been
written to since it was read from memory, and a "Least Recently Used" tag that
identifies which of the two cache lines should be overwritten if another address that
maps there is accessed by the CPU.
• For the purposes of cache operation, memory is divided into pages of 2 megabytes,
composed of 4 kB sub-pages (1024 words of 32 bits).
• A cache line is marked as "dirty" when the CPU writes to an address which is
currently in the cache. In this case, the data in the "real" memory no longer reflects the
actual value. The entire cache line is marked as dirty when any element within that
cache line is written.
• A cache miss is defined as a read or write by the CPU to an address in memory which
is not currently in the cache.
UM10208_1
User manual
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 01 — 5 September 2006
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