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A
B
C
D
GND
PS2
2
1
1
1
VCC
GND
PS1
I/O
2
1
J1
Z75_1
BNC_EDGE
LAYOUT NOTE:
C8
4.7uF
Z75_n: W=20MIL, ZO=75+/-5%
C9
0.1uF
C1
4.7uF
2
VCC
C10
0.01uF
GND
R2
75
GND
Z75_2
R3
220
GND
2
C2
4.7uF
Z75_3
VCC
Z75_4
GND
C12
0.1uF
C3
1uF
SCK
MOSI
MISO
SSb
GND
1
2
3
4
5
6
7
8
9
10
11
12
VCC
GND
C13
0.1uF
RSVD
VCCTX
VCCTX
RSVD
RSVD
RSVD
RSVD
BNC_IO
RSVD
RSVD
RSVD
RSVD
R6
Zero
GND
GND
SCK
MOSI
MISO
SS
GND
SPI HEADER
JP1
1
2
3
4
5
6
HDR_6
VCC
3
GND
TX_ENABLE
MOSI
SCK
C11
1uF
3
36
35
34
33
32
31
30
29
28
27
26
25
VCC
R1
GND
715
U1
LMH0387
RREF
VEE
SDI
SDI
VEE
VEE
VCCRX
MISO
SDO
SDO
SS
VEE
R7
OPEN
GND
C14
0.1uF
GND
MISO
SSb
VCC
VCC
R5
100
D1
LED-GREEN
VCC
SD/HD
SDHD
TX ENABLETX_ENABLE
CD
CDb
VCC
CD
R4
300
4
JP2
1
3
5
7
2
4
6
8
HDR_4X2
4
GND
RREF
SDHD
48
47
46
45
44
43
42
41
40
39
38
37
RSVD
RSVD
RSVD
TERM_TX
SD/HD
VCCTX
RSVD
VEE
TX_EN
MOSI
SCK
VEE
RSVD
RSVD
RSVD
RSVD
TERM_RX
SPI_EN
VEE
AEC+
AECCD
CDTHRESH
VEE
13
14
15
16
17
18
19
20
21
22
23
24
GND
ZDIFF100N_1
ZDIFF100P_1
ZDIFF100P_2
ZDIFF100N_2
C4
4.7uF
C5
4.7uF
C6
4.7uF
C7
4.7uF
Z50_1
Z50_2
Z50_3
Z50_4
5
Title:
SDI-
J2
SMA_R_EDGE
SDI+
J3
SMA_R_EDGE
GND
SDO+
J4
SMA_R_EDGE
SDO-
J5
SMA_R_EDGE
GND
Z50_n: W=40MIL, ZO=50+-5%
LAYOUT NOTE:
LAYOUT NOTE:
6
ZDIFF100P_n, ZDIFF100N_n: DIFFERENTIAL 100OHM IMPEDANCE
http://www.national.com
6
© Copyright, National Semiconductor, 2010
Sheet: 1 of 1
Rev: A
SD387 Evaluation Board for the LMH0387
Size: B
Date: 4/19/2010
File: SD387.SchDoc
5
A
B
C
D