Download DE2 Development and Education Board User Manual

4.2 General Design Flow
This section will introduce the general design flow to build a project for the DE4 board via the DE4
System Builder. The general design flow is illustrated in the Figure 4–1.
Users should launch DE4 System Builder and create a new project according to their design
requirements. When users complete the settings, the DE4 System Builder will generate two major
files which include top-level design file (.v) and the Quartus II setting file (.qsf).
The top-level design file contains top-level verilog wrapper for users to add their own design/logic.
The Quartus II setting file contains information such as FPGA device type, top-level pin assignment,
and I/O standard for each user-defined I/O pin.
Finally, Quartus II programmer must be used to download SOF file to DE4 board using JTAG
interface.
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