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DIO24
UsertsManual
ffi
Inc.
RearTimeDevices,
"AccessingtheAnalog World'k
nrnt/
L'IL'L+
User'sManual
ffi
INC.
REALTIMEDEVICES,
PostOfficeBox906
16804
StateCollege,Pennsylvania
Phone:(814)234-8087
FAX:(81a)234-5218
Published by
Real Time Devices, Inc.
P.O. Box 906
StateCollege, PA 16804
Copyright @ 1992 by Real Time Devices, Inc.
All rights reserved
Printedin U.S.A.
Rev.B 9352
Thbleof Contents
INTRODUCTION....
WhatComes
WhenYou NeedHelp..
CHAPTER 1 - BOARD SETTINGS
Factory-Configured
SwitchandJumperSettings
...............1-3
P3 - IntemrptandIntemrptChannels(FactorySetting:GND Connected;
IntemrptChannelsDisabled).....14
P4- IntemrptSourceSelect(FactorySetting:EXT)...........
.............14
P5 - 8254TimerrcounterClock Sources(Facory Settings:CLK0-XTAL, CLKI-OUT0, CLK2-OUTI)....1-5
Sl - BaseAddress@acorySetting:300hex(768decimal) .................
..............1-6
52 - BufferBypassSwitch(FacorySening:OPEN(Not Bypassed))
...................
....................1-7
Fl - Extern
Pull-up/Pull-down
Resistors
on DigitalVO Lines.....
.........1-8
CHAPTER 2 _ BOARD INSTALLATION
ConnectingtheTimer/CounterI/O......
Connectingthe External
Runningthe24DIAGDiagnostics
Prograrn
CHAPTER 3 - HARDWARE DESCRIPTION
DigitalVO, 8255ProgrammablePeripheral
Interface......
CHAPTER 4 _ BOARD OPERATION AND PROGRAMMING
BA + 0:
BA + l:
BA+ 2:
BA + 3:
BA + 4:
BA + 5:
PPIPortA - Digial VO (ReadlMrite)
................
PPIPortB - DigitalVO (ReadlMrite)................
PPIPortC - DigitalVO (ReadflVrite)
................
8254PPIConrol Word(WriteOnly) ...........
IRQ Enable(WriteOnly) ..........
(ReadlTVrite)
IntemrptStatus/Clear
BA + 7: Reserved
BA + 8: 8Zi4Timer/Counter
0 (Read,AMrite)
BA + 9: 8254Timer/Counter
1 (Read/TVrite)
BA + l0: 8254Timer/Count€r
2 (ReadflMrite)
BA+ 1l: 8254ConnolWord(Writeonly)...........
Clearing
andSettingBitsin a Port...........
2-'..
......24
.......................24
3-l
......................3-3
.............4.1
...............4-3
...............4-3
...............4-3
.......................44
......................4-5
................4-5
...............4-6
...............4-6
.............4-6
.......4-6
......................4-8
What Is
IntemrptController..
8259Programmable
IntemrptMaskRegister(It"R) ..........
(EOI)Command
End-of-Intemrpt
WhatExactly}lappensWhenanIntemrptOccurs?
UsingIntemrptsin YourPrograms..........
Writing an IntemrptServiceRoutine(ISR)
Savingthe StartupIntemrptMaskRegister(IMR) andIntemrptVector
Restoringthe StartupIMR andIntemrptVecor
CommonIntemrptMistakes
...............4-l
I
......................4-11
......4-11
.....................4-l
I
................4-12
..........4-13
.....4-14
C and Pascal
APPENDIX A - DIO24 SPECIFTCATIONS
A-l
APPENDIX B - VO CONNECTORPIN ASSIGNMENTS
APPENDIXC _ COMPONENTDATA SHEETS
B-l
c-l
APPENDIX D - WARRANTY
D-l
LIST OF ILLUSTRATIONS
1-1
r-2
r-3
I4
l-5
l-6
t-7
1-8
1-9
1-10
2-l
3-1
4-l
BoardLayoutShowingFactory-Configured
Settings...................
IntemrptandIntemrptChannelJumper,P3 ...............
PullingDowntheIntemrptRequest
Line
IntemrptSourceSelectJumper,P4..............
8254Timer/Counter
ClockSourceJumpers,
P5................
8254Timer/CounterCircuitBlock Diagram
BaseAddress
Switch,Sl ................
PortC BufferCircuitry
Port A Pull-up/Pull-down
ResistorCircuitry
AddingPull-upsandPull-downsto SomeDigital VO Lines
P2 andP6 I/O ConnectorPin Assignments
DIO24BlockDiagram
8254Timer/CounterCircuit Block Diagram
tu.
..................
1-3
14
...............
.............14
.........1-5
........1-5
........1-6
......................1-6
....................1-8
........1-9
.....1-9
..........24
.....................3-3
......4-10
INTRODUCTION
i-1
The DIOZ seriesboardsaregeneralpurposedigital I/O boardfor usein the IBM PC/XTIAT or compatible
computer.The DIO24 serieshastwo models:the DIO24-I and ttreDIO?4-Z with timer/counters.Installedwithin a
singleshortor full-size expansionslot in the computer,the DIOZ features:
. ?4TTLICMOS 8255-basedprogrammable
digitalVO lines,
. Directconnectionto optn-zzllO systemmodules,
. Bufferedoutputsfor highdriving capability,
. Threel6-bit timer/counters
@IO%-2 modelonly),
. Optionalpull-up/pull-downresistors,
. Simple I/O or srobed VO operation,
. Softwareenabledintemrpts(IRQ2-IRQ7),
. Assembly,BASIC, Turbo Pascal,andTurbo C sourcecode;diagnosticsprogram.
The following paragraphsbriefly describethe major functionof the board.A moredetaileddiscussionof board
functionsis includedin Chapter3,HardwareOperation,andChapter4,Board OperationandProgramming.The
boardsetupis describedin Chapterl,Board Seuings.
Digital VO
The DIO24 has24 TTL/CMOS-comparibledigiral VO lines which canbe directly interfacedwirh exrernal
devicesor signalsto senseswirchclosures,trigger digital events,or activatesolid-staterelays.Theselines are
providedby the on-board8255programmableperipheralinterfacechip. The 8255canbe operatedin oneof two
modes:Mode 0 or Mode 1. To ensurehigh driving capacity,CMOS buffers areinsalled. TTL buffers are available
on request.
Padsfor installing andactivatingpull-up or pull-down resistorsareincludedon the board.Installationproceduresaregivenat theendof Chapterl, Board Seuings.
8254Timer/Counter(DlO24-2)
4n8254 programmableinterval timer containsthree 16-bit"8 MtIz timer/countersto supporta wide rangeof
timing and countingfunctions.The clock, gat€,andoutputpins for eachof ttretimer/countersare availableat I5, a
20-pin on-boardbox headerconnector.
What ComesWith Your Board
You receivethe following itemsin your DIO24 package:
. DIO? -L orDIO24-2 (with timer/counters)interfaceboard
. Softwareand diagnosticsdiskeuewith Assembly,BASIC, Turbo Pascal,andTurbo C sourcecode
. Ijser's manual
pleasecall RealTime Devices'CustomerServiceDepartmentat
If any item is missingor damaged,
(814)234-8087.If you requireserviceoutsidetheU.S.,contactyorn localdistributor.
Board Accessories
In addition to the items includedin your DIO2'4package,Real Time Devicesoffers a full line of accessories.
Call your local distributor or our main office for moreinformationabouttheseaccessories
and for help in choosing
the bestitems to supportyour board'sapplication.
Accessoriesfor the DIO24 includethe TB50 terminalboardand XB50 prototype/terminalboardfor prototype
developmentandeasysignalaccess,the XO50 cableassemblyfor direct connectionn opn-22 systems,and the
TW50 twistedpair wire flat ribbon cableassemblyfor externalinterfacing.
i-3
UsingThis Manual
This manualis intendedto helpyou installyour newboardandget it runningquickly,while alsoproviding
enoughdetailabouttheboardandits functionsso thatyou canenjoymaximumuseof its featuresevenin themost
complexapplications.
We assumethatyou alreadyhavean understanding
of dataacquisitionprinciplesandthatyou
cancustomizetheexamplesoftwareor write yourown applications
programs.
When You NeedHelp
This manualand the exampleprogramsin the softwarepackageincludedwith your boardprovide enough
informationto properly useall of theboard'sfeatures.If you haveany problemsinsulling or using this board,
(814)234-8087,duringregularbusinesshours,eastemstandardtime or
contactour TechnicalSupportDepartment,
qrtern daylighttime,or senda FAX requestingassistance
to (814)234-5218.Whensendinga FAX request,please
includeyotu company'snameandaddress,
your narne,your telephonenumber,anda brief descriptionof the
problem.
i4
CHAPTER1
BOARD SETTINGS
The DIO24 board hasjumper and switch settingsyou can
changeif necessaryfor your application.The board is factoryconfigured with the most often used settings.The factory settings
are listed and shown on a diagram in the beginning of this chapter.
Should you need to changethesesettings,use theseeasy-to-follow
instructions before you install the board in your computer.
Note that DIP switch 52 has beenprovided to bypassthe
Port C buffers and allow Mode 1 operationof the 8255.
Also note that by installing resistor packs ar three locations
around the 8255 PPI and solderingjumpers in the desiredlocations
in the associatedpads, you can configure your digital VO lines to
be pulled up or pulled down. This procedureis explained at the end
of this chapter.
1-1
Factory-ConfiguredSwitch and Jumper Settings
Table 1-1 lists the factory settingsof the user-configurablejumper and switches on the DIO24 board. Figure 1-l
shows the board layout and the locations of the factory-setjumpers. The following paragraphsexplain how to
changethe factory settings.Pay special attention to the setting of Sl, the baseaddressswitch, to avoid address
contention when you first use your board in your system.
Table1-l - FactorySettings
Switch/
Jumper
FactorySettings
(Jumperslnstalled)
FunctionGonirolled
P3
Connects1 of 6 interrupt
sourcesto an interrupt GND(groundfor buffer)
channel;pullstri-statebufferto ground(GND)for connected;
interrupt
channels
multipleinterrupt
applications
disabled
P4
Selectsthe interrupt
source
EXT(externalinterrupt)
P5
Setsthe clocksourcesfor thethree8254
timer/counters
OC0-TC2)
CLK0-XTAL;
CLKl-OUTO;
(allthree
CLK2-OUT1
timer/counters
arecascaded)
S1
Sets the base address
300 hex (768 decimal)
s2
BypassesPortC buffersfor Mode1 operation
Open(buffersnot bypassed)
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Settings
133
P3 - Interrupt and Interrupt Channels(FactorySetting: GND Connected;Interrupt ChannelsDisabled)
This headerconnector,shownin Figure1-2,letsyou connectan interruptsourceselectedon P4 o an intemrpt
channel,IRQ2throughIRQ7.To connecttheintemrptsourceto an interruptchannel,you mustinstall a jumper
acrossthe desiredIRQ channel.
Ns,l)$lDlDf-(J
.ooo.o?
P3
Fig. 1-2-
a
E
HOOOOa
Interupt and lnterruptChannelJumper,P3
The rightmostpair of pins on P3, labeledG, areprovidedso that you can install a jumper which connectsa
1 kilohm pulldown resistorto theoutputof a high-impedance
tri-statedriver whichcarriestheintemtptrequest
signal.This pull-downresistordrivestheintemrptrequestline low wheneverinterruptsarenot active.So,whenever
an intemrptrequestis made,thetri-statebufferis enabled,forcingtheoutputhigh andcausingan intemrpt.You can
monitor the intemrpt statustlrough bit 0 in the statusword (I/O addresslocationBA + 5). After the intemrpt has
beenserviced,theclearcommandreturnsthe IRQ line low, disablingthe ni-statebuffers,andpulling theoutputlow
again. Figure1-3showsthis circuit.Becausetheintemrptrequestline is drivenlow only by thepull-downresistor,
you canhavetwo or moreboardswhich sharethesameIRQ channel.You cantell which boardissuedtheintemrpt
requestby monitoringeachboard'sIRQ statusbit.
NOTE: Whenyou usemultipleboardsthatsharethesameintemrpt,only oneboardshouldhavetheG ground
jurnperinstalled.Therestshouldbe disconnected.
Wheneveryou operatea singleboard,theG jumpershouldbe
installed.
INT
SOURCE
IRO STATUS
IN T E R R U P T
Fig. 1-3 -
PullingDownthe InterruptRequestLine
P4 - Interrupt SourceSelect(Factory Setting: EXT)
This headerconn@tor,shownin Figure14, letsyou connectoneof six interruptsourcesfor intemrptgeneration. Thesesourcesare:OT0, OT1, andOT2, whicharethethree8254timer/counter
outputsavailableon the
DlO24-2model;PC3,which is theINTRA signalfrom ttre8255PPI;PCO,which is theINTRB signalfrom the
8255PPI; and EXT, an extemalintemrpt you canroute onlo the bard ttrough theP2 I/O connector.To connectan
intemtptsource,placethejumperacrossthedesiredsetof pins.Note thatonly ONE int€rruptsourcecanbe activatedat a time.
t4
Fa'tC)OFCr|
il88bb5
?.oo.o
oooooo
Fig. 1-4-
InterruptSourceSelectJumper,P4
P5 - 8254Timer/Counter Clock Sources(Factory Settings: CLK0-XTAL, CLKI-OUT0, CLK2-OUTI)
This headerconnector,shownin Figurel-5, letsyou selecttheclock sourcesfor the 8254ttmerlcounters,
TC0,
TCl, andTC2 which areon theDlO24-2model.Thefactorysettingcascades
all threetimer/counten,with theclock
sorucefor TC0 being ttreon-board8 MHz oscillator,the outputof TCOproviding the clock for TCl, and ttreoutput
of TCI providing the clock for TC2. You canconnectany or all of tle sourcesto an externalclock input throughthe
P6 on-boardI/O connector,or you cansetTCI andTC2 to be clockedby the8 MlIz oscillator.Figure1-6showsa
block diagramof the timer/countercircuitry to help you with theseconnections.
NOTE: Wheninstallingjumperson this header,makesurethatonly onejumperis installedin eachgtoupof
two or threeCLK pins.
P5
Usedwith OlO24-2modelonly
EI
XTAL
il
El
OUTO
EXTCLKO
XTAL
EXTCLKl
OUTl
XTAL
EXTCLK2
Fig.1-5-8254 Timer/Counter
P5
ClockSourceJumpers,
l-5
I 8254
TtilEn/
COUNTER
o
i---;----:
I
I
I
CLK
GATE
|
I
iTv
i
ON.BOARD
I/O CONNECTOR
P6
I
I
| cr-xoS
I
I
|
|
i
i
I r4&1x.su''""
XTAL(8 MHz)
p l n r o EXT CLK O
EXT GATEO
T/C OUT O
OUT
a
I
ct-xrI
TIIIER/
COU1{TEF
I
CLK
11I
GATE
OUT
TtnEnt
couNTER
2
CLK
+5V
I
I
I oulr
I
J
PIN13
EXTCLK 1
PIN I!
EXTGATE1
PIN
T/C OUT 1
I
I
I
C LK2
tt
EXTCtK 2
r{M{+Sv
I
GATE
EXT GATE 2
T/C OUT 2
OUT
L:I
Fig. 1-6 -8254 Timer/CounterCircuitBtock Diagram
51-
BaseAddress(FactorySetting:300hex (768decimat))
Oneof the most.commoncausesof failure whenyou arefirst trying your boardis addresscontention.Someof
your computer'sI/O spaceis alreadyoccupiedby internalI/O and otherperipherals.When the DIO24 board
asemptsto useVO addresslocationsalreadyusedby anotherdevice,contentionresultsand the boarddoesnot work.
To avoidthisproblem,theDIO24 hasan easilyaccessible
DIP switch,Sl, which letsyou selectany oneof 32
startingaddresses
in the computer'sVO. Shouldthe facory settingof 300 hex (768 decimal)be unsuitablefor your
system,you can selecta different baseaddresssimply by settingthe switchesto any value shownin Table 1-2.The
tableshowsthe switch settingsand their correspondingdecimalandhexadecimal(in parentheses)
values.Make sure
that you verify the orderof the swirchnumberson the switch (l through5) beforesettingthem.When the swirches
arepulled forward, theyare OPEN,or set to logic l, aslabeledon the DIP switchpackage.When you set tle base
addressfor your board,recordtle value in the tableinsidethe backcover.Figure 1-7 showsthe DIP swirchset for a
baseaddressof 300hex (768decimal).
Fig.1-7- BaseAddressSwitch,51
l-6
Table1-2- BaseAddressSwltchSettlngs,Sl
BaseAddress
Declmal/ (Hex)
SwltchSetting
54321
SwltchSettlng
54321
srz| (200)
00000
BaseAddress
Declmal/(Hex)
768/ (300)
528| (210)
00001
784| (3r0)
1000r
s44tQ20)
560tQ30)
00010
800/ (320)
816/ (330)
10010
s76| (240)
00100
10100
s92| (2so)
00101
832I (34O)
848/ (350)
608tQ60)
6U t (270)
00110
864/ (360)
l0ll0
880/ (370)
l0ltl
&0 tQ80)
01000
896/ (380)
11000
656| (290)
672l(2A0)
01001
9r2 I (390)
11001
01010
928/ (340)
11010
688/ (2Bo)
7o4l (2Co)
01011
11011
01100
9M t(380)
960/ (3C0)
720t(2D0)
01101
976 tQDO)
736l(zBo)
01
7s2I (2F0)
01111
992t(3E0)
1oo8/ (3Fo)
00011
001
I
10
10000
10011
10101
11100
I 101
1i110
11111
0=closed,1=opefi
52 - Buffer BypassSwitch (Factory Setting:OPEN (Not Bypassed))
Whenoperatingthe 8255 in Mode 1, the lines of Port C function ascontrol lines, someasoutputsand someas
inputs.When usingMode 1, thePort C buffersmustbe removedandbypassedto allow the Port C lines to be
individuallysetasinputsor outputs.Figure1-8showsthePortC buffers,andthe following stepstell you how to
configurethe boardfor Mode I operation.
To removebuffering from Port C:
1. CloseDIP switchesI through8 on 52.
2. RemoveU3 from theboard.
3. RemoveU4 from the board.
CAUTION: Remember,wheneveryou closetheswitches,be sure to removethebuffers,U3 andU4, from the
board.Failure to do so may damagefte board.
Fl - External +S-voltFuse
This I amperefuseprotectsthe+5 volt line availableat VO connectarY2,pin 49 from drawingtoo much
curent anddamagingsystemequipment.
PC7
PC6
PC5
PC4
PC3
PC2
PCl
PC0
Fig.1-8- PortC BufferCircuitry
Pull-up/Pull-downResistorson Digital VO Lines
The 8255programmableperipheralinterfaceprovides24puallelTTL/CMOS compatibledigital VO lines
which canbe interfacedwith externaldevices.The lines aredivided into four grcups: eight Port A lines, four Port C
Lower lines, eight Port B lines, and four Port C Upperlines. You can install andconnectpull-up or pull-down
resistorsfor any or all of thesefour groupsof lines. You may want to pull lines up for connectionto switches.This
will pull the line high whentheswitchis disconnected.
Or, you may wantto pull downlinesconnected!o relays
which control nrning motorson andoff. Thesemotorsturn on whenthe digital lines controlling themare high.
To usethe pull-up/pull-downfeature,you mustfirst install l0 kilohm resistorpacksin any or all of the four
locationsaroundthe 8255,labeledPA, PB, PCL, andPCH.PA andPB takea 10-pinpack,andCL andCH take
6-pinpacks.Figure l-9 showstheselocations.
After theresistorpacksareinstalled,you mustconnecttheminto thecircuit aspull-upsor pull-downs.Locate
the three-holepadson theboardnearthe resistorpacks.They are labeledG (for ground)on one endand V (for Vcc)
on tle otherend.The middleholeis common.PA is for Port A, PB for Port B, CL is for Port C Lower,andCH is
for Port C Upper.Figure I -9 showsa blowup of the padsfor Port A. To operateaspull-ups, soldera jumper wire
betweenthe commonpin (middlepin of the three)andtheV pin. For pull-downs,soldera jumperwire betweenthe
commonpin (middlepin) andtheG pin. For example,Figure1-10showsPort A lineswith pull-ups,Port C Lower
with pull-downs,andPortC Upperwith no resistors.
1-8
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Fig.1-9- PortA Pull-up/Pull-down
8255
(
oJ
,o",
(PA0.7)
\
t
f
L O W E"B<
"or,
(PAo-3)
[
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U P P E R<
(PA4-7)
|\
to SomeDigitall/O Lines
andPull-downs
Fig.1-10- AddingPull-ups
CHAPTER2
BOARD INSTALLATION
TheDIO24 is easyto installin your IBM PCIKT/AT. It canbe
placedin any slot,shortor full-size.This chaptertells you step-bystephow to install andconnectthe board.
After you haveinstalledthe boardandmadeall of your connections,you canturn your systemon andrun the 24DIAG board
diagnosticsprogramincludedon your examplesoftwaredisk to
verify thatyour boardis working.
2-1
Board Installation
Keepthe boardin its antistaticbag until you arereadyto insall it in your computer.When removingit from the
bag,hold theboardat theedgesanddo not touchthecomponents
or connectors.
Beforeinstalling the boardin your computer,checkthejumper seuings.ChapterI reviewsthe factory settings
and how to changethem.If you needto changeany settings,refer to the appropriateinstructionsin Chapter1.Note
that incompatiblejumper settingscanresult in unpredictableboardoperationanderratic response.
Also notethat the P2tlO connectormountingbrackethasan oversizedcutout to allow spacefor running the
cableto 20-pin on-boardconnectorP6 throughthe sameVO slot. If you want to run both cablesthroughthe same
slot, you mustmaketheseconnectionsbeforeinstalling the board.
To install the board:
1. Turn OFF the power to your computer.
2. Removethe top coverof the computerhousing(refer o your owner's manualif you do not alreadyknow
how to do this).
3. Selectany unusedshortor full-sizeexpansionslotandremovetheslot bracket.
4. Touch the metalhousingof the computerto discharyeany staticbuildup andthenremovettreboardfrom its
antisatic bag.
5. Holding the boardby its edges,orient it so that its cardedge(bus)connectorlines up with the expansionslot
connectorin thebottom of the selectedexpansionslot.
6. After carefully positioningilre boardin the expansionslot so that the card edgeconnecroris restingon the
computer'sbusconnector,gentlyandevenlypressdownon theboarduntil it is securedin theslot.
NOTE: Do not force the boardino the slot. If the boarddoesnot slide ino place,removeit and try again.
Wiggling the boardor exertingtoo muchpressurecanresultin damageto the boardor to the computer.
7, Af,terthe boardis installed,securethe slot bracketbackinto placeandput t}recoverbackon your computer.
The boardis now readyO be connectedvia the externalVO connectorat the rear panelof your computer.
2-3
External VO Connections
Figure2-1 showstheDIO24'sn. IP connectorpinoutandP6 on-boardI/O connectorpinout.Referto these
diagramsasyou makeyour I/O connections.
FOo
EXTII{T
PCI
DIGITALOID
Fql
DICITA OiD
FGI
orGrTlL oro
PC0
PCt
PC2
PC3
PC4
PC5
PC6
PC7
POr
DIGITA GII)
PCs
DIGITA GII)
DIGITALG}ID
EXT CLK O
PO8
DIGITALGII)
EXT GATE O
T/C OUT O
FC?
DIGITALGII)
EXT CLK I
PBO
IXGITAL OII)
T/C OUT 1
EXT CLK 2
PEI
DlclT L cr€
EXT GATE 2
T/C OUT 2
PA2
T'IGITA GIT)
PB3
DIGITA GT€
PA
OGITAL GIO
FBt
DIOITALGTO
P88
DICITALCiD
PB7
IIIGITAL GI{'
FAO
DIGITALCiD
PAl
D|c|rat
PA2
DIGITAL OIO
FA3
DIGITAL GIO
PA.
otolTAL olt
OIGITALGND
EXT GATE 1
DIGITALGIID
P6
20-pinon-boardl/O connector
Glo
FA6
0GITA CIS
FA6
DtorTA cro
PA7
DIGITA GII)
+5 VOTTS
DIGITA GIO
P2
50-pinl/Oconnector
Fig.2-1- P2 and P6 l/O ConnectorPin Assignments
Connectingthe Digital UO
The DIO24 is designedfor direct connectionto indusry sandard opto-z2isolatedI/O racksand system
modules.Eachdigital I/O line on P2 hasa digital ground,asshownin Figure2-1.For all digital I/O connections,
rhe
high sideof an externalsignalsourceor destinationdeviceis connectedto the appropriatesignalpin on the I/O
connector,and the low sideis connectedto the DIGITAL GND. A cableto provide direct connectionto opto-22
systemsis availableas an accessoryfrom RTD.
Connectingthe Timer/Counter UO
Externalconnectionsto the timer/counterson the DIO24-2 modelcanbe madeby connectingthe high side of
the extemaldeviceto the appropriatesignalpin on on-boardconnectorP6 and the low side to a P6 DIGITAL GND.
Connectingthe External Interrupt
The DIO24 can receivean externallygeneratedintemrpt signal,EXTINT, throughI/O connectorP2, pin 2 and
route it to an IRQ channelthroughon-boardheaderconnectorsP3 andP4. Interruptgenerationis enabledthrough
software.When intemtpts are enabled,a rising edgeon the EXTINT line will causethe selectedIRQ line to go high,
and the IRQ statusbit will changefrom 0 to 1. The pulseappliedto the EXTINT pin shouldhavea durationof at
least100nanoseconds.
Runningthe 24DIAG DiagnosticsProgram
Now that your boardis readyto use,you will want to try it out. An easy-to-use,menu-drivendiagnostics
program,24DIAG,is includedwith your examplesoftwareto helpyou verify your board'soperation.You canalso
usethis progxamto makesurethat your curent baseaddresssettingdoesnot contendwith anotherdevice.
24
CHAPTER 3
HARDWAREDESCRIPTION
This chapterdescribesthemajorfeaturesof theDIO24's 8255
baseddigital VO and 8254timer/counters.
This chapteralsodescribesthe hardware-selectable
intemrpts.
3-l
TheDIO24providesbuffereddigital I/O lines,asshownFigure3-1.In addirion,theDIO24-2model
providesthree16-bit timer/counters.This chapterdescribesthe hardwarewhich makesup the digital I/O circuiry,
timer/counten,and hardware-selectable
intemrpts.
l!-tl
Fig.3-1-DlO24 BlockDiagram
Digital VO, 8255ProgrammablePeripheralInterface
The 8255programmableperipheralinterface@PI)canbe easily configuredto solvea wide rangeof digital
real-worldproblems.This high-performanceTTL/CMOS compatiblechip has24 parallelprogrammabledigital VO
linesdividedinootwo goups of 12lineseach:
Group A - Port A (8 lines) andPort C Upper (4 lines);
GroupB - Port B (8 lines) andPort C Lower (4 lines).
Eachgroup can be programmedfor Mode 0 or Mode I operation.Do not try to useMode 2 operation! The
DIO2/1doesnot supportMode 2. Whenoperatingin Mode 1, the on-boardbuffers mustbe removedfrom the Port C
lines. This procedureis describedin Chapter1 in the 52 DIP swirchdiscussion.The DIO24 operatingmodesare:
Mode 0 - Basicinput/output.Lets you usesimpleinput and outputoperationfor a port Datais written to or
readfrom the specifiedport.
Mode 1 - Strobedinput/output.Lets you transferVO datafrom Port A or Port B in conjunctionwith strobesor
handshaking
signals.
Thesemodesare detailedin the 8255Data Sheet,reprintedfrom Intel in Appendix C.
Thebidirectionalbufferson the 8255'sI/O linesmonitorthe 8255controlword to automaticallysetttreir
direction.Hardwarechangesto the buffer circuiry is requiredonly when using Mode 1, wherethe Port C buffers
mustbe removedas describedin Chapter1.
3-3
Timer/Counters
An 8254programmableinterval timer providesthreel6-bit, 8 MlIz timer/countersto supporta wide rangeof
timing andcountingfunctions.Thesetimer/counters
canbe cascaded
or usedindividuallyfor manyapplications.
Eachtimer/counter
hasnro inputs,CLK in andGATE in, andoneoutput,timer/counterOUT. Theclock
sotucesfor the timer/counters
canbe selectedusingjumperson headerconnectorP5 (seeChapter1). The timer/
counterscanbe programmedasbinary or BCD down countersby writing ttreappropriatedatato the commandword,
asdescribedin Chapter4. The commandword also lets you setup the modeof operation.The six programmable
modesare:
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Event Counter(Interrupton TerminalCount)
Hardware-ReriggerableOne-Shot
RateGenerator
SquareWave Mode
Softrvare-Triggered
Srobe
llardware TriggeredSrobe (Reriggerable)
Thesemodesare detailedin the 8254DataSheet,reprintedfrom Intel in AppendixC.
Interrupts
The DIO24 canuseanyoneof six signalsourcesto generateintemrps.Thesesourcesare:OT0, OT1, andOT2,
which arethethree8254imer/counteroutputsavailableon the DIO24-2model;PC3,which is theINTRA signal
from the 8255PPI; PC0,which is the INTRB signalfrom the 8255PPI; andEXT, an externalintemrpt you can
routeonto theboardthroughtheY2I/O connector.Chapter1 tellsyou how to setthejumperson infemrptheader
connectorsP3 and P4, andChapter4 providessomeprogramminginformation.
J-+
CHAPTER 4
BOARDOPERATIONAND PROGRAMMING
This chaptershowsyou how to prognm anduseyour DIO24
board.It providesa completedescriptionof the VO mapanda
detaileddescriptionof programmingoperationsto aid you in
programming.Theexampleprogrirmsincludedon thedisk in your
boardpackagearelistedat theendof this chapter.Theseprognms,
writtenin TurboC, TurboPascal,Assembly,andBASIC, include
sourcecodeto simptfy your applicationsprogramming.
4-l
4-2
Definingthe VO Map
TheVO mapfor theDIO24 is shownin Table4-1 below.As shown,theboardoccupies12consecutive
VO port
locations.Thebaseaddress(designated
asBA) canbe selectedusingDIP switch51 asdescribedin Chapterl,
Board Settings.
This switchcanbe accessed
withoutremovingtheboardfrom thecomputer.Thefollowing sections
describethe registercontentsof eachaddressusedin the VO map.
Table4.1 - DlO24t/O Map
ReglsterDescription
ReadFunctlon
WrlteFunctlon
Address'
(Declmal)
8255PPIPortA
ReadPortA digitalinputlines ProgramPortA digitaloutput
lines
BA+0
8255PPIPortB
ReadPortB digitalinputlines ProgramPortB digitaloutput
lines
B A +1
8255PPlPortC
ReadPortC digitalinputlines ProgramPortC dighaloutput
lines
BA+2
8255PPlControlWord
Not used
ProgramPPIconfiguration
BA+3
lRQ Enable
Not used
Enableand disableinterrupt
generation
BA+4
Interrupt
Status/Clear
Readstatusof interrupt
Glearinterrupt
BA+5
Reserved
B A +6
Reserved
B A +7
S254Timerl0ounter
0
ReadTCOcountvalue
LoadTCOcountregister
BA+8
8254Timer/Counter
1
ReadTC1countvalue
LoadTC1countregister
BA+9
8254Timer/Counter
2
ReadTC2countvalue
LoadTC2countregister
B A +1 0
8254ControlWord
' BA = BaseAddress
Not used
Programcontrolregister
BA+ 11
BA + 0: PPI Port A - Digital VO (Read/Write)
Transferstle 8-bit Port A digital input anddigital ouput databetweenthe boardand an exremaldevice.A read
transfersdatafrom the externaldevice,throughY2, andino PPI Port A; a write transfersthe written datafrom
Port A throughP2 to an extemaldevice.
BA + 1: PPI Port B - Digital VO (ReadAilrite)
Transfersthe 8-bit Port B digital input and digital outputdatabenveenthe boardand an externaldevice.A read
transfersdatafrom the externaldevice,throughY2,andinto ppl port B; a write ftansfersthe written daa from
Port B throughY2ta an extemaldevice.
BA + 2: PPI Port C - Digital VO (Read/Write)
Transfersthe two 4-bit Port C digital input anddigital outputdatagroups@ort C Upper andport C Lower)
betweentheboardandan extemaldevice.A readtransfersdatafrom theextemaldevice,throughy2,and,intoppl
Port C; a write transfersthe written datafrom Port C throughP2 to an externaldevice.
4-3
BA + 3: E255PPI Control Word (Write Only)
Whenbit 7 of this word is setto 1, a write programs$rePPI configuration.Bit 6 mustalwaysbe set to 0
(Mode2 operationis not supportedby the DIO?'/). The tablebelow showsthe control words for the 16possible
Mode 0 Port VO combinations.
D7
D6
D5
D4
D3
D2
D1
DO
-1
r
ModeSet F'"s
i
1 = active
|
I
I
ll
l"
rde Seler:t
t= mode
= mode
t t = mode i
i3l
I
I
I
I
I
I
Port A
0 E output
1 = input
PortC Upper
0 = output
j
f'*pj
I
L
Portc
t C Lower
o = output
oul
1 = input
inp
|
|
|
PorrB
0 = oulput
1 = inPut
|
|
I
ModeSelect
0=mode0
1=mode1
GroupB I
--_t
"t --r
8255Port l/O Flow Dlrectionand ControtWords,Mode0
GroupA
GroupB
ControlWord
Porl A
Port C
Upper
Port B
Port C
Lower
Binary
Decimal
Hex
Output
Output
Outpul
Output
10000000
128
80
Output
Output
Outpul
Input
10000001
129
81
Outpul
Output
Input
Output
10000010
130
82
Output
Output
lnput
lnput
10000011
131
83
Output
Input
Output
Output
10001000
136
88
Output
Input
Output
Input
10001001
137
89
Output
lnput
lnput
Output
10001010
138
8A
Output
lnput
lnput
Input
10001011
139
8B
Input
Output
Output
Output
10010000
144
90
Input
Output
Output
Input
10010001
14s
91
Input
Outpul
Input
Output
10010010
146
92
lnput
Output
Input
lnput
10010011
147
93
lnput
Input
Output
Output
10011000
152
98
Input
Input
Output
Input
10011001
153
99
Input
Input
Input
Oulput
10011010
154
9A
Input
lnput
Input
Input
10011011
155
9B
44
Whenbit 7 of this word is setto 0, a write canbe usedto individually pro$am the Port C lines.
D7
D6
D5
D4
SeUReset
FunctionBit
0 = aclive
02
D3
D1
DO
Blt SsUReset
0=setbitto0
1=solbittol
Bit Select
000= PCO
001= PCI
010=PC2
011= PCa
100=PC4
10'l= PC5
110=PC6
1 1 1= P C 7
For example,if you wantto setPort C bit 0 to 1, you would setup thecontrolword so thatbit 7 is 0; bits 1, 2,
and 3 are0 (this selectsPCO);andbit 0 is I (this setsPCOto l). The conrrolword is setup like this:
0xxxo001
Sets PCOto 1:
(writtento BA +3)
D7
D6
SeUReset
FunctlonBir
D5
D4
D3
D2
X = don'tcare
D1
DO
Set PCO
Blt Salect
000= PCo
BA + 4: IRQ Enable (Write Only)
Enablesand disablesintemrpt generation.Writing a "l" enablesintemrpt generation;writing a "0" disables
intemrpt generation.
InterruptEnablE/Disable
0 = interrupt
disabled
1 = interruptenabled
BA + 5: Interrupt Status/Clear(Read/Write)
A read showsthe statusof the int€rrupt(bit 0 only) asdefinedbelow. A write clearsthe intemrpt (datawritten is
irrelevant).Eachtime theintemrptstatusbit goeshigh,a write shouldfollow to clearthebit.
InterruptStatus
0 = nointerrupt
1 = interrupt
hasoccurred
4-5
BA + 6: Reserved
BA + 7: Reserved
BA + t: t254 Timer/Counter 0 (ReadAMrite)
A readshowsthe countin the count€r,anda write loadsthecounterwith a newvalue.Countingbeginsassoon
asthecountis loaded.
BA + 9: 8254Timer/Counter I (ReadAMrite)
A readshowsthecountin the counter,anda write loadsthecount€rwith a newvalue.Countingbeginsassoon
asthe count is loaded.
BA + 10: t254 Timer/Counter 2 (Read/Write)
A readshowsthe countin tle counter,anda write loadsthe counterwith a new value.Countingbeginsas soon
asthecountis loaded.
BA + 11.: 8254Control Word (Write Only)
Accessesthe 8254control registerto directly control the threetimerrcounters.
07
D6
D5
D4
D3
D2
D1
DO
BCD/Binary
0 = binary
1=BCD
CounterSelEct
SelEc
00 = Counter0
01 = Counter1
10= Counler
2
11 = rsadbacksetting
Read/Load
gg = latchingoperation
01 = read4oad
LSBonly
10 = read/load
MSBonly
11= read/load
LSB,thenMSB
4-6
CounterModeSelect
000= Mode0, sventcount
001= Mode1, programmable
1-shot
x10= Mode2, rategenerator
xl 1 = fvle6s3, squarewaverategenerator
100= Mode4, software-triggered
strobe
101= Mode5, hardware-triggered
strobe
Programming the DlO24
This sectiongivesyou somegeneralinformationaboutprogrammingand the DIO24 board,and then walks you
throughthe major DIO24 programmingfunctions.Thesedescriptionswill help you as you usethe exampleprogramsincludedwith the board.All of the programdescriptionsin this sectionusedecimalvaluesunlessotherwise
specified.
The DIO24 is programmedby writing to andreadingfrom theconect I/O port locationson 0reboard.TheseI/O
portsweredefinedin theprevioussection.Most high-levellanguages
suchasBASIC,Pascal,C, andC++, andof
courseassemblylanguage,makeit very easyto read/writethesepors. The tablebelow showsyou how to readfrom
and write to VO ports using somepopularprogramminglanguages.
Language
Read
Data= INP(Address)
BASIC
Wrlte
OUTAddress,Data
Data= inportb(Address) outportb(Address,
Data)
TurboC
Turbo Pascal
Assembly
Dala:= Port[Address]
Port[Address]:= Data
movdx, Address
in al,dx
movdx, Address
moval, Data
outdx,al
In addition to beingable o read/writethe I/O ports on the DIO24, you mustbe able o perform a variety of
operationsthat you might not normally usein your programming.The tablebelow showsyou someof the operators
in this section,with an exampleof how eachis usedwith Pascal,C, andBASIC. Notethatthe modulus
discussed
operatoris usedto retrievethe leastsignificantbyte (LSB) of a two-byteword, and the integerdivision operatoris
usedto retrievethe mostsignificantbyte (MSB).
Language
c
Modulus
IntegerDlvlslon
ot
a=bohc
a=b/C
AND
&
a=b&c
OR
I
a=blc
Pascal
MOD
a:=bMODc
DIV
a:=bDlVc
AND
a:=bANDc
OR
a:=bORc
BASIC
MOD
a=bMODc
\ (backslash)
a=b\c
AND
a=bANDc
OR
a=bORc
Many compilershavefunctionsthat canread/writeeittrer8 or 16 bia from/to an I/O port. For example,Turbo
PascalusesPort for 8-bit port operationsandPortW for 16bits, Turbo C usesinportb for an 8-bit readof a port
andinport for a 16-bitread.Be sure to useonly 8-bit operationswith the DIO24!
4-7
Clearing and SettingBits in a Port
Whenyou clearor set one or morebits in a port, you mustbe careful that you do not changethe statusof the
otherbits. You canpreservethe statusof all bits you do not wish to changeby properuseof the AND and OR
binary operators.Using AND and OR, singleor multiple bits canbe easilyclearedin one operation.
To clear a singlebit in a port, AND the cunent valueof ttreport wittr the valueb, whereb = 255 - 26'.
Example: Clear bit 5 in a port. Readin the currentvalueof the port, AND it with 223
(223= 255 - 25),andthenwrite theresultingvalueto theport. In BASIC, thisis programmedas:
V : fNP(PortAddress)
V=VAND223
OUT PortAddress, V
To set a singlebit in a port, OR the currentvalueof the port with the valueb, whereb = 2u,.
ExamDle: Setbit 3 in a port.Readin thecurrentvalueof theport,OR it with 8 (8 = 23),andthen
write the resultingvalueto theport. In Pascal,this is programmedas:
V := Port [PortAddress],V:=VOR8,.
Port [PortAddress] := V,'
just aseasily.To clear multiplebits in a port"
Seningor clearingmorethanonebit at a time is accomplished
AND the currentvalue of the port with the valueb, whereb = 255 - (ttresumof the valuesof the bits to be cleared).
Note that the bits do not haveto be consecutive.
Example: Clearbits 2 ,4,and6 in a porr Readin tfie currentvalueof theport, AND it with 171
(171= 255 -22 - f - 2u),andthenwrite theresultingvalueto theport. In C, this is programmed
as:
v = inportb (port_address),.
v=vAt?]-;
outportb (port_address, v) ;
To set multiple bits in a port, OR the currentvalueof the port with the valueb, whereb = tle sumof the
individual bits to be set.Note that the bits to be setdo not haveto be consecutive.
Frramnle: Setbis 3, 5, and7 in a port. Readin the currentvalueof the port" OR it wittr 168
(168= 23+ 25+ 2),and thenwrite theresultingvalueback!o thepon. In assemblylanguage,ttris
is programmedas:
mov dx, PortAddress
in al, dx
or al, 168
out dx, alOften, assigninga rangeof bits is a mixture of settingand clearingoperations.You can setor clear eachbit
individually or usea fastermethodof frst clearingall the bits in the rangethensettingonly thosebits that mustbe
setusingthe methodshownabovefor settingmultiple bits in a port. The following exampleshowshow this twostepoperationis done.
Examnle: Assignbits 3,4, and5 in a port to 101(bits 3 and5 set,bit 4 cleared).First,readin the
port andclearbis 3,4, and5 by ANDing themwith 199. Thensetbits 3 and5 by ORingthem
with 40, andfinally write theresultingvaluebackto ttrepon. In C, this is programmed
as:
4-8
v = inportb(port_address) ;
v=v&199;
v:v
| 40;
outportb (port_address, v) ;
A final note: hn't be intimidatedby the binary operatorsAND and OR andtry to useoperatorsfor which you
havea betterintuition. For instance,if you aretemptedo useadditionand subtractionto setand clearbits in place
of themethodsshownabove,DON'T! AdditionandsubEaction
may seemlogical,but theywill not work if you try
to cleara bit that is alreadyclearor seta bit that is alreadyset.For example,you might think that to setbit 5 of a
port, you simply needto readin theport, add32 (25)to that value,and thenwrite the resultingvalueback to theport.
This works fine if bit 5 is not alreadyset.But, what happenswhenbit 5 is alreadyset?Bits 0 to 4 will be unaffected
and we can't sayfor surewhat happensto bits 6 and7, but we cansayfor surethat bit 5 endsup clearedinsteadof
being set A similar problemhappenswhen you usesubtractionto cleara bit in placeof the methodshownabove.
Now that you know how !o clear andsetbits, we arcreadyto look at the programmingstepsfor the DIO24
boardfunctions.
Initializing the 8255PPI
Beforeyou canoperatetheDIO24,the8255mustbe initialized.This stepmustbe executedeverytime you strrt
up, reset,or rebootyoru computer.
The 8255is initializedby writing theappropriate
controlword to I/O port BA + 3. The contentsof your control
you
word will vary, dependingon how
want to configureyour VO lines.Use the control word descriptionin the
previousVO mapsectionto help you programtheright value.Rememberthat theDlO24 cannotuseMode 2. In the
examplebelow,a decimalvalueof 128setsup the 8255so thatall I/O linesareMode0 outpus.
D7
D6
D5
D4
D3
D2
D1
DO
Digital VO Operations
Oncethe 8255is initialized,you canusethedigitalI/O linesto controlor monitorexternaldevices.
Timer/Counters
An 8254proglammableintervaltimer providesthreel6-bit, 8-MHz timer/counters
for timing andcounting
functionssuchas frequencymeasurement,
eventcounting,and intemrpts.All threetimerrcountersare cascadedat
thefactory.Figure4-l showsthetimer/counter
circuiny.
Eachtimer/counterhasnvo inputs,CLK in andGATE in, andoneoutput, timer/counterOUT. They canbe
programmedasbinary or BCD down countersby writing the appropriatedatato the commandword, as describedin
the I/O mapsectionat the beginningof this chapter.
Oneof two clock sources,the on-board8-MI{z crystal or an externalclock routedttrroughon-boardI/O
connectorP6 canbe selectedas the clock input to eachtimer/counter.In addition,the timer/counterscanbe cascadedby connectingTCO'soutputto TCI's clock input andTCI's outputto TC2's clock inpur The diagramshows
how theseclock sourcesare connectedto the timerrcounters.
An externalgatesourcecanbe connectedto eachtimer/counterthroughP6. When a gateis disconnected,an onboardpull-up resistorautomaticallypulls the gatehigh, enablingthe timer/counter.
The ouput from eachtimer/counteris availableatP6, whereit can be usedfor intemrpt generationor for
countingfunctions.
The timer/counterscan be programmedO operatein one of six modes,dependingon your application.The
following paragraphsbriefly describeeachmode.
4-9
iffi--- I
I
TIMER/
COUIITER
0
;
I
I
I
P5
lnrrnA
;--'-r
I
I
-
ttl
I
EXTGATEO
I
I
I
I
-I
+5V
I
GATE
EXTCLK 1
PIN 13
r-f--
CLK
T/C OUT 0
PIN
ii","ffiH
OUT
EXTCLK O
PIN
+5V
OUT
TIIIER/
couNTER
1
I
I
|
'1-!-
CLK
GATE
ON.BOARD
I/O CONNECTOR
P6
EXTGATE1
T/C OUT 1
PIN
ttl
| 1",,,f-*4
TIIIER/
couNTER
2
CLK
--J
tl
EXTCLK 2
r4Ml+5
v
l
GATE
PIN I
ouT
EXTGATE2
T/C OUT 2
Fig.4-1 -8254 Timer/Counter
CircuitBlockDiagram
Mode 0' Event Counter flnterrupt on Terminal Count).This modeis typicallyusedfor eventcounting.
While the timer/counter
countsdown,theoutputis low, andwhenthecountis complete,it goeshigh.The output
stayshigh until a new Mode 0 conrol word is written to the timer/counter.
Mode I, Hardware-RetriggerableOne-Shot.The outputis initially high andgoeslow on theclockpulse
following a triggerto begintheone-shotpulse.Theoulputremainslow until thecountreaches0, andttrengoeshigh
andremainshigh until the clock pulseafter the next rigger.
Mode 2' Rate Generator.This modefunctionslike a divide-by-Ncounterandis typicallyusedBogeneratea
real-timeclock intemrpt.The outputis initially high,andwhenthe countdecrements
to 1, tle outputgoeslow for
oneclockpulse.Theoutputthengoeshigh again,ttretimer/counter
reloadstheinitial counl andtheprocessis
repeated.
This sequence
continuesindefinitely.
Mode 3' SquareWave Mode. Similarto Mode2 exceptfor theduty cycleoutput,this modeis typicallyused
for baudrategeneration.Theoutputis initially high,andwhenthecountdecrements
to one-halfis initial count"the
outputgoeslow for theremainderof thecount.Thetimer/counter
reloadsandtheoutputgoeshighagain.This
processrepeatsindefinitely.
Mode 4' Software-TriggeredStrobe.The outputis initially high.Whentheinitial countexpires,theoutput
goeslow for oneclock pulseandthengoeshigh again.Countingis "triggered"by writing theinitial counl
Mode 5' Hardware Triggered Strobe(Retriggerable).The outputis initially high.Countingis triggeredby
therising edgeof thegateinput.Whenthe initial counthasexpired,theoutputgoeslow for oneclockpulseand
thengoeshigh again.
4-10
Interrupts
- lVhat Is an Interrupt?
An intemrpt is an eventthat causesthe processorin your computero temporarilyhalt its currentprocessand
executeanotherroutine.Upon completionof the new routine,control is retumedto tle original routine at thepoint
whereits executionwasintemrpted.
Intemrptsare very handyfor dealingwith asynchronous
events(eventsthat occurat lessthanregularintervals).
Keyboardactivity is a goodexample;your computercannotpredictwhen you might pressa key and it would be a
wasteof processortime for it o do nothingwhile waiting for a keysfioketo occur.Thus,tle intemrpt schemeis
usedand tle processorproceedswith othertasks. Then,whena keystrokedoesoccur,the keyboard'intemrpts' the
processor,and the processorgetsthekeyboarddat4 placesit in memory,and thenreturnso what it wasdoing
beforeit was intemrpted.Other commondevicesthat useintemrptsare modems,disk drives,and mice.
Your DIO24 boardcan intemrpt the processorwhenoneof the six intemrpt sourcesis enabled.By usingthese
intemrpts,you can write sofnrarettrateffectively dealswith real world events.
- Interrupt RequestLines
To allow different peripheraldevicesto generateintemrptson the samecomputer,the PC bushaseight different
intemtpt request(RQ) lines. A transitionfrom low to high on one of theselines generatesan intemrpt request
which is handledby thePC's intemrpt controller.The intemrpt controllercheckso seeif intemrptsare to be
acknowledgedfrom that IRQ and,if anotherintemrpt is alreadyin progress,it decidesif the new requestshould
supersedethe one in progressor if it hasto wait until the onein progressis done.This prioritizing allows an
intemrpt to be intemrptedif the secondrequesthasa higherpriority. The priority level is basedon the numberof the
IRQ; IRQOhasthehighestpriority, IRQI is second-highest,
andso on ttrroughIRQ7,which hasthelowest.Many of
theIRQsareusedby thestandardsystemresources.
IRQ0 is usedby the systemtimer,IRQ1is usedby thekeyboard,IRQ3 by COM2,IRQ4by COMI, andIRQ6 by ttredisk drives.Therefore,it is importantfor you to know
which IRQ lines areavailablein your systemfor useby the DIO24 board.
- 8259ProgrammableInterrupt Controller
The chip responsiblefor handlinginterruptrequestsin the PC is the 8259ProgrammableIntemrpt Connoller.
To useinterrupts,you will needto know how to readand setthe 8259's intemrpt maskregister(IMR) and how to
sendtheend-of-intemrpt(EOI) commandto the8259.
- Interrupt Mask RegisterOMR)
Eachbit in theintemrptmaskregister(IMR) containsthemaskstatusof an IRQ line; bit 0 is for IRQ0,bit I is
for IRQI, andsoon. If a bit is set (equalto 1), thenthecorresponding
IRQ is maskedandit will not generatean
intemrpt.If a bit is clear (equalto 0), thentheconesponding
IRQ is unmaskedandcangenerateintemrps.The
IMR is programmedthroughport 21H.
IRQT
IRQ6
IRQ5
IRQ4
IRQ3
IRQ2
IRQl
IRQO
t/O Port 21H
For all blts:
(enabled)
0 = IRQunmasked
1 = IRQmasked(disabled)
- End-of-Interrupt (EOI) Command
After an intenuptserviceroutineis complete,ttre8259intemrptcontrollermustbe notified.This is doneby
writing the value 20H to I/O port 20H.
- What Exactly HappensWhen an Interrupt Occurs?
Undersrandingthe sequenceof eventswhenan intemrpt is riggered is necessaryto properly write software
intemrpthandlers.Whenan interruptrequestline is drivenhigh by a peripheraldevice(suchastheDIO24),the
4-l I
intemrpt conroller checksto seeif intemrptsareenabledfor ttratIRQ, and thencheckso seeif other in@mrptsare
activeor requestedand determineswhich intemrpt haspriority. The intemrpt controller then intemrptstheprocessor.The curent codesegment(CS),instructionpointer (IP), and flags arepushedon the stackfor storage,and a new
CS and IP are loadedfrom a tablethat existsin the lowest 1024bytesof memory.This tableis referredto asfte
intemrpt vectortableandeachentry is calledan intemrpt vector.Oncethe new CS andIP areloadedfrom the
intemrpt vectortable,the processorbeginsexecutingthe codelocatedat CS:IP.When the intemtpt routine is
completed,the CS, IP, and flags that werepushedon the stackwhenthe intemrpt occunedarenow poppedfrom the
stackandexecutionresumesfrom the point whereit wasintemtpted.
- Using Interrupts in Your Programs
Adding intemrptsto your softwareis not asdifficult as it may seem,and what they add in termsof performance
is often worth the effort. Note, however,that althoughit is not that hardto useintemrpts,the smallestmisake will
often leadto a systemhangthat requiresa rebool This canbe both frusrating and time-consuming.But" after a few
tries,you'll get thebugsworkedout andenjoythebenefis of properlyexecutedintemrps.
- Writing an Interrupt ServiceRoutine (ISR)
The frst stepin addingintemrptsto your softwareis o write the intemrpt serviceroutine (ISR). This is the
routine that will automaticallybe executedeachtime an interruptrequestoccurson the specifiedIRQ. An ISR is
different than standardroutinesthat you write. First, on entrance,theprocessorregistersshouldbe pushedonto the
stackBEFORE you do anythingelse.Second,just beforeexitingyour ISR, you mustcleartheintemrptstatusof the
DlO24 andwrite an end-of-interrupt
commandto the8259connoller.Finally,whenexitingtheISR, in additionto
poppingall the registersyou pushedon enEance,you mustusetlre IRET instructionandnot a plain RET. The IRET
automaticallypopsthe flags,CS,andIP thatwerepushedwhentheintemrptwascalled.
If you find yourselfintimidatedby intemrpt programming,take heart.Most Pascaland C compilersallow you
to identify a procedure(function) asan intemrpt type andwill automaticallyaddtheseinstructionsto your ISR, with
one importantexception:mostcompilersdo not auomatically addthe end-of-intemrptcommandto ttreprocedure;
you mustdo this yourself.Otherthanthis andthefew exceptions
below,you canwrite your ISRjust like
discussed
any otherroutine.It can call otler functionsandproceduresin your programandit canaccessglobal data.If you are
writing your first ISR, we recommend
thatyou sticko thebasics;just somethingthatwill convinceyou thatit
works,suchas incrementinga globalvariable.
NOTE: If you are writing an ISR usingassemblylanguage,you areresponsiblefor pushingandpopping
registersand using IRET insteadof RET.
Therearea few cautionsyou mustconsiderwhenwriringyour ISR.The mostimportantis, do not useany
DOS functionsor routinesthat call DOS functionsfrom within an ISR. DOS is not reentranqthatis, a DOS
function cannotcall itself. In typical programming,this will not happenbecauseof the way DOS is wrinen. But
whataboutwhenusingintemrpts?Then,you couldhavea situationsuchasthisin yourprogram.If DOS functionX
is beingexecutedwhenan intemrptoccursandtheintemrptroutinemakesa call to DOS functionX, thenfunction
X is essentiallybeing called while it is alreadyactive.Sucha reentrancyattemptspellsdisasterbecauseDOS
functionsare not written to supportit. This is a complexconceptandyou do not needto understandit Justmake
surethatyou do not call any DOS functionsfrom within your ISR.Theonewrinkle is that,unfortunately,it is not
obviouswhich library routinesincludedwith your compileruseDOSfunctions.A mle of thumbis thatroutines
which write to the screen,or checkthe statusof or readthe keyboard,andany disk VO routinesuseDOS and should
be avoidedin your ISR.
The sameproblemof reentrancyexistsfor manyfloating point emulatorsaswell, meaningyou may haveto
avoid floating point (real) math in your ISR.
Notethat theproblemof reentrancyexists,no matt€rwhatprogramminglanguageyou arc using.Evenif you
arewriting your ISR in assemblylanguage,DOSandmanyfloatingpoint emulatorsarenot reenEant.Of course,
therearewaysaroundthis problem,suchasthosewhich involvecheckingto seeif any DOS functionsarecurrently
activewhenyour ISR is called,but suchsolutionsarewell beyondthescopeof this discussion.
The secondmajorconcernwhenwriting your ISR is to makeit asshortaspossiblein termsof executiontime.
Spendinglongperiodsof time in your ISR may meanthatotherimportantintenuptsarebeingignored.Also, if you
4-12
spendtoo long in your ISR, it may be calledagainbeforeyou havecompleredhandlingthe first run. This often leads
to a hangthat requiresa rebool
Your ISR shouldhavethis structue:
' Pushanyprocessorregistersusedin your ISR.Most C andPascalintemrptroutinesautomaticallydo this for
you.
. Put thebodyof yourroutinehere.
. Clear the intemrpt bit on the DlO24 by wriring any valueto BA + 5.
' IssuetheEOI commandto the 8259intemrptcontrollerby wriring 20Hta porr20H.
' Pop all registerspushedon enEance.Most C andPascalintemrpt routinesautomaticallydo this for you.
The following C andPascalexamplesshowwhat the shell of your ISR shouldbe like:
In C:
void interrupt
ISR(void)
T
t
/* Your code goes here. Do not
outportb(BaseAddress
+ 5, 0);
outportb(0x2o,
0x20);
*/
use any DOS functions!
*/
/* Clear DIO24 interrupt
/* Send EOf commandto 8259 */
)
In Pascal:
Procedure ISR; Interrupt;
begin
{ Your code goes here. Do not
Port[BaseAddress
+ 5] :: 0;
Port[$20]
:: 920;
end;
use any DOS functions!
}
{ Clear DIO24 interrupt
}
I S e n d E O I c o m m a n dt o 8 2 5 9 ]
- Savingthe Startup Interrupt Mask Register(IMR) and Interrupt Vector
The next.strepafter witing the ISR is to save0restartupstateof the intemrpt maskregisterand the intenupt
vectorthatyou will be using.The IMR is locatedat I/O port 21H. Theintemrptvectoryou will be usingis located
in the intemrpt vector tablewhich is simply an arny of 256-bit (4-byte)pointersand is locaredin rhefint 1024
bytesof memory(Segment= 0, Offset= 0). You canreadthis valuedirectly,but it is a betterpracticeto useDOS
function 35H (get intemrpt vector).Most C andPascalcompilersprovide a library routine for readingthe value of a
vertor. The vectorsfor the hardwareintemrptsarev@tors8 through 15,whereIRQ0 usesvector 8, IRQI uses
vector9, andsoon. Thus,if theDIO24 will be usingIRQ3,you shouldsavethevalueof intemrptvectorI l.
Before you install your ISR, temporarilymaskout the IRQ you will be using.This preventsthe IRQ from
requestingan intemrpt while you areinstalling andinitializing your ISR. To maskthe IRQ, readin ttrecurrentIMR
at VO port 2lH and set the bit that correspondsto your IRQ (remember,settinga bit disablesintemrptson that IRQ
while clearinga bit enablesthem).The IMR is arrangedso thatbit 0 is for IRQ0,bit I is for IRQI, andso on. See
the paragraphentttledIntenupt MaskRegister(IMR) earlierin this chapterfor help in determiningyour IRQ's bit.
After settingthe bit, write the new valueto I/O port 2tlt.
With the startupIMR savedand the intemrptson your IRQ temporarilydisabled,you canassignthe intemlpt
vector to point to your ISR. Again, you can overwritethe appropriateentry in the vector tablewith a direct memory
write,but this is a badpractice.Instead,useeitherDOSfunction25H (setintemrptvector)or, if your compiler
providesit, the library routine for settingan intemrpt vector.Rememberthat vector 8 is for IRQ0, vector 9 is for
IRQI, andsoon.
If you needto programthe sourceof your intemrpts,do that next.For example,if you are usingthe programmableinterval timer to generateintemrpts,you mustprogmmit to run in the propermodeand at the properrate.
Finally,clearthebit in theIMR for theIRQ you areusing.This enablesintemrptson the IRQ.
4-13
- Restoringthe Startup IMR and Interrupt Vector
Beforeexiting your program,you mustrestorethe intemrpt maskregisterandintemrpt vectorsto the statethey
werein whenyour progam started.To restorethe IMR, write the valuethat was savedwhen your programstarted
to VO port 21H.Restoretheintemrptvectorthatwassavedat startupwith eitherDOS function35H (getintemrpt
vector),or usethelibrary routinesuppliedwith your compiler.Performingthesetwo stepswill guarantee
thatthe
intemtpt statusof your computeris the sameafter runningyour prognm as it wasbeforeyour programstarted
running.
- CommonInterrupt Mistakes
. Rememberthat hardwareintemrptsarenumbered8 through15,eventhoughthe correspondingIRQs are
numbered0 through7.
. Two of themostcommonmistakeswhenwriting an ISR areforgettingto cleartheintemrptstatusof the
DIO24 andforgeningto issuetheEOI commandto ttre8259intemrptconroller beforeexitingthe ISR.
BxamplePrograms
Includedwitl the DlO24 is a setof exampleprogramsthat demonstratethe useof manyof the board's features.
Theseexamplesarein writtenin C, Pascal,Assembly,andBASIC. Also includedis an easy-to-use
menu-driven
diagnosticsprogram,24DIAG, which is especiallyhelpful whenyou arefirst checkingout your boardafter installation.
Before usingthe softwareincludedwith your board,makea backupcopy of the disk. You may makeasmany
backupsasyou need.
C and PascalPrograms
Theseprogramsare sourcecodefiles so that you caneasilydevelopyour own customsoftwarefor your DlO24
board.
Digital VO:
DIGITAL
Simplepro$am the showshow to readand write the digital I/O lines.
Timer/Counters:
TIMER
A shortprogramdemonstratinghow to programthe 8254for useasa timer.
BASIC Programs
Theseprogramsincludeboth sourcecodefiles andexecutablefiles so that you canrun themon your DIO24.
progrms aresetup to look for theboardat a baseaddress(BA) of 300 hex(768decimal).If
All of theexecutable
you changethe baseaddressof theboard,you mustalso changethe BA in your programs.
Digital VO:
DIGITAL
Simpleprogramtheshowshow to readandwrite thedigital I/O lines.
Timer/Counters:
TIMER
A shortprogramdemonstratinghow to programthe 8254for useasa timer.
4-r4
APPENDIX A
DTO24SPECIFICATIONS
A-l
A-2
DlO24 Characteristics rypical
@25'c
lnterface
Switch-seleclable
baseaddress,
l/Omapped
Jumper-selectable
interrupts
DlgltalyO .............
CMOS82C55
Oplo-22compatible
Number
of fines
......................24
Logiccompatibility
............
.............TTUCMOS
(Configurable
withoptionall/O pull-up/pull-down
resistors)
High-level
outpulvo|tage...................
....................4.2V,
min
Low-levsl
outputvoltage..................
..................0.45V,
max
High-level
inputvoltage.
.2.2Y,min1'5.SV,
max
inputvohage
Low-level
.-0.3V,min;0.8V,max
High-leveloutput
current,
lsource
buffer:-12mA,max;
.................CMOS
TTLbuffer:-16mA,max
Low-leveloutput
current,
1sink..........
..............CMOS
buffer:24mA,max;
TTLbutfer:64 mA.max
Inputloadcurrent
pA
............1'10
Inputcapacitance
pF
..............
.....................10
Inputcapacitance,
pF
C(|N)@F=1MHz
................
..................10
Outputcapacitance,
pF
C(OUT)<@F=1MHz
.......20
Timer/Counters
...........
Three16-bitdowncounters
6 programmable
operating
modes
Counter
inputsource
Counteroutputs
Countergatesource..
...........CMOS
82C54
clock(8 MHz,max)or
...........
External
on-board8 MHzclock
Available
usedas PC interrupts
externally;
gateor alwaysenabled
........External
GurrentRequirements
194mA@ +5 volts
Connectors
P2 - 50-pin rightangle shroudedbox header
P6 - 20-pin box header
Size
(99mm
Shortslot- 3.875"H
x 5.25"W
x 134mm)
A-3
A4
APPENDIX B
UOCONNECTORPIN ASSIGNMENTS
B-1
B-2
VO ConnectorP2:
PCo
ETTINT
PCl
DIGITAL GND
PC2
DIGITAL GND
PC3
DIGITAL GNO
PC4
TXGITALGND
PCs
TXGITALGND
PC6
DIGITAL GNO
PC7
UGITAL GND
PBO
DIGITAL GND
PBl
DIGITAL GNO
Pg!2
DIGITAL GND
P83
I'IGITA
GND
P84
DGITAL GND
P85
OIGITAL GND
P86
DIGITAL GND
P87
DIGITAL GND
PAO
I}GITAL GND
PAl
TXGITALGND
pN2
DIGITAL GND
PA3
DIGITAL GND
PA4
DIGITA GND
PA5
DIGITA GNO
PA6
OGITAL GNO
PA7
DIGITAL GNO
+5 VOLTS
OIGITAL GNO
On-boardConnectorP6:
PC0
PCI
PC2
PC3
PC4
PC5
PC6
PC7
DIGITALGND
EXT CLK O
EXT GATEO
T/C OUT O
EXTCLK 1
EXT GATE 1
T/C OUT 1
EXT CLK 2
EXT GATE2
T/C OUT 2
DIGITALGND
DIGITALGND
B-3
B4
APPENDIX C
COMPONENTDATASHEETS
lntel82C55AProgrammable
PeripheralInterface
DataSheetReprint
intel'
82C55A
INTERFACE
PERIPHERAL
CHMOSPROGRAMMABLE
I Control Word Read-BackCapablllty
r Direct Blt Set/ResetGaPability
. 2.5 mA DC Drive Capabllltyon all l/O
Port Outputs
r AvailableIn 40-PinDIPand 44-PinPLCC
r Availablein EXPRESS
- StandardTemperatureRange
- ExtendedTemperatureRange
I Compatlblewith all Intel and Most
Other Microprocessors
r Hfgh Speed,"Zero Walt State"
Operationwith 8 MHz8086/88and
80186/188
) 24 Programmablel/O Plns
I Low PowerCHMOS
r GompletelyTTL Compatible
The Intel82C55Ais a high-performance,
CHMOSversionof the industrystandard82554generalpurpose
programmable
lt provides
l/O devicewhichis designedfor usewithall Inteland mostothermicroprocessors.
programmed
in 2 groupsot 12 andusedin 3 majormodesof operation.
24llo pinswhichmaybe individually
The82C55Ais pincompatible
withthe NMOS8255Aand8255A-5.
in setsof 4 and I to be inputsor outputs.ln
ln MODE0, eachgroupof 12llo pinsmaybe programmed
4 pinsareused
to haveI linesof inputor output.3 of theremaining
MODE1,eachgroupmaybe programmed
busconfiguration.
for handshaking
and intenuptcontrolsignals.MODE2 is a strobedbi-directional
The 82C55Ais fabricatedon lntel'sadvancedCHMOSlll technologywhichprovideslow powerconsumption
with performance
equalto or greaterthanthe equivalentNMOSproduct.The 82C55Ais availablein 40-pin
DfP and 44-9inplasticleadedchipcanier(PLCC)packages.
r e3 i ! 3 r i 3 i 3 r l
IESEI
I
@
t
t0
DI
02
Drt
Lc
0,a
D5
06
m
tl
t2
tl
la
t5
t6
l,
dorl6ats
SSEERIEETES
ldcluqrlg
231256-3 1
'
t2c56
231256-1
Flgure 1.82C55ABlock Dlagram
231256-2
Figure2.82C55APlnout
Oagramsare lor pin r€l€renceonly.Package
saz€sar€ not to scale.
3-124
mcr
S.pLnb.? 10t7
Iumb.c 23l25a0oa
82C55A
Table1.PlnDescrlpilon
Symbol
PAg-o
PlnNumber
Dlp
PLCC
1-4
2-5
PORTA, PINS0-3: Lowernibbleof an g-bitdataoutputlatch/
butfer and an 8-bit data input latch.
6
I
READ CONTROL: This inout is low durino CFI I raor{ nnara}iaaa
7
I
CHIPSELECT:
A towon thisinputenablesthe82CSSA
to
respondto R'DandWFIsignals.H'DandWRareignored
otherwise.
SystemGround
ADDRESS:
Theseinputsignals,
in conjunction
R-DanOWF,
controlthe sel€ctionof oneof thethreeportsor thecontrol
wordregisters.
5
6
GND
7
I
lot-o
8-9
g-to
PCt-t
10-13 11,13-15
ato
PCo-s
PBo-z
14-17
16-19
18-25
vo
vo
RESET
35
20-22,
24-28
29
30-33,
35-38
39
WF
36
40
I
37-40
41-44
t/o
Vcc
Dz-o
PAz-q
NC
26
27-34
Nameand Functlon
t/o
HD
6
|
Type
1,12,
23,34
vo
I
A1
Ae
0
0
Ri0
0
0
WF 6
lnput Operaflon(Read)
PortA-DataBus
0
1
1
PortB-DataBus
1
0
1
PortC-DataBus
1
1
0
1
- DataBus
ControlWord
OutputOperailon(Wrtte)
0
0
1
0
0
DataBus- PortA
0
1
1
0
0
DataBus- PortB
1
0
1
0
0
DataBus- PortC
1
1
1
0
0
DataBus- Control
DlsableFunctlon
x
x
x
x
1
DataBus-3-State
X
x
1
1
0
DataBus-3-State
C,
PINS
4-7: Uppernibbteof an 8-bitdataourputtatch/
l9lT
butferandan B-bitdatainputbutfer(nolatchfor inpui).rtris port
canbe dividedintotwo4-bitportsunderthe modecontror.Each
4-bitportcontainsa 4-bitlatchandit canbe usedfor thecontrol
signaloutputsandstatussignalinputsin conjunction
withports
A andB.
I
0
0
0
0
PORTC, PINS0-3: Lowernibbleof porr C
PORTB, Plils 0-7: An 8-bitdataoutputtatch/bufferandan 8_
bit datainputbutfer.
SYSTEM
POWER:f 5VpowerSuppty.
DATA BUS: Bi-directional,tri-statedata bus lines,connectedto
systemdata bus.
RESET:A highon thisinputclearsthecontrolregisterandall
portsaresetto the inputmode.
WRITECONTROL:
Thisinputis lowduringCpUwrite
operations.
POFT A, PINS4-7: Uppernibbleof an 8-bitdata outputlatch/
lffer and an 8-bit data input latch.
No Connect
3-125
intef
82Cs5A
82C55AFUNCTIONAL
DESCRIPTION
General
peripheralinterface
The82G55Ais a programmable
devicedesignedfor usein Intelmicrocomputer
systsms. lts functionis that of a generalpurposel/O
componentto int€rfaceperipheralequipment
to the
microcomputer
syst€mbus.The functionalconfigurationof the 82C55Ais programmed
by the system
sottwareso that normallyno externallogicis necessaryto interfaceperipheraldevicesor structuras.
DataBuc Buffer
This3-statebidirectionalS-bit
butleris usedto interface the 82C554to the systemdata bus. Datais
transmitted
or receivedby the butferuponexecution
of inputor outputinstructionsby the CPU.Control
words and statusinformationare also transferred
throughthe datrabusbutfer.
Read/Wrlteand Control Loglc
The functionof thL block is to manageall of the
internaland externaltransfersof both Data and
Controlor Statuswords.lt acceptsinputsfromthe
CPUAddressandControlbusses
andin tum,issues
commandsto bothof the ControlGroups.
Group A and Group B Controls
The functionalconfigurationof each port is programmedby the systemssottware.In essence,the
CPU"outputs"a controlwordto the 82G55A.The
controlwordcontainsinformationsuchas "mode",
"bit set", "bit rgs€t", etc., that initializesthe funcof the 82C55A.
tionalconfiguration
Eachof the Controlblocks(GroupA and GroupB)
Control
fromthe Read/Write
accepts"commands"
Logic,receives"control words" from the internal
to its asdatabusand issuesthe propercommands
sociatedports.
ControlGroupA - PortA andPortC upper(C7-C4)
ControlGroupB - PortB andPortC lower(C3-C0)
The controlword registercan be both writtenand
readas shownin the addressdecodetable in the
pin descriptions.
Figure6 showsthe controlword
lormatlor both Readand Write operations.When
the controlwordis read,bit D7 willalwaysbe a logic
"1", as thisimpliescontrolwordmodeinformation.
PortgA, B, and C
The82C55Acontainsthr€eI'bit ports(A,B, andG).
All can be configuredin a widevarietyof functional
by the syst€msottwarebut eachhas
characteristics
its own specialfeaturesor "personality"to further
enhancethe powerandflexibilityof the 82C55A.
Port A. One 8-bitdataoutputlatch/butferand one
8-bit input latch butfer,Both "pull-up" and "pulldown"bus holddevicesare presenton PortA.
Port B. One 8-bit data input/outputlatch/butfer.
Only"pull-up"busholddevicesare presenton Port
B.
Port C. One 8-bitdata outputlatch/butferand one
8-bitdata inputbutfer(no latchfor input).This port
can be dividedinto two 4-bitportsunderthe mode
control.Each4-bitport containsa 4-bit latchand it
canbe usedfor the controlsignaloutputsandstatus
withportsA and B. Only
signalinputsin conjunction
"pull-up"bus holddevicesare pr€senton PortG.
for
SeeFigure4 for thebus-holdcircuitconfiguration
PortA, B, and C.
3-126
irttgr
82C55A
fo
it
al
raltt
Flgure3.82c55ABlock DlagramShowlngDataBusBufferand Bead/Wrltecontrol LogtcFunclons
it8Er
IITER'IAL
DATA I}I
rxTElflat
oATAOUT
EXTENilAL
poFr I,c
FIN
DITEEilAL
o?A
.lloTE:
231256-4
Portpinsloadedwithmorethanz0 pF capacitance
maynot havetheirlogiclevel guaranteed following a hardware reset.
Flgure4. Port A, B, C, Bus-holdConfiguration
3-127
intef
82C55A
82C55AOPERATIONAL
DESCRIPTION
coa{rnoLwoiD
q
ModeSelectlon
or
Dt
o.
D3
D2
Dl
q
J
Thereare threebasicmodesof operationthat can
be selectedby the systemsottware:
Mode0 - Basicinput/output
Mode1 - Strobedlnput/output
Mode2 - Bi-directional
Bus
Whentheresetinputgoes"high"allportswillbesel
to the inputmodewith all24 porllinesheldat a logic
"on€" level by the internalbus hold devices(see
Figure4 Note). After the reset is r€movedthe
82C55Acan remainin the inputmodewithno additionalinitialization
required.
Thiseliminates
the need
lor pullupor pulldowndevicesin "all CMOS"designs.Duringthe executionof the systemprogram,
anyof the othermodesmaybe selectedby usinga
single output instruction.This allows a single
82C55Ato servicea varietyof peripheraldevices
with a simplesottwaremaintenance
routine.
/
onott!
\
t'Ont C lLOWCnl
l.ltft l
0. OUT'UT
foFt t
l.lltlPUT
0. OUIruT
rooE tat€c?lor
0. ilOOE0
I .lrOOEI
/
ctorra
\
rcnT c iltrEil
l. II{'UT
0.oUTrut
The modesfor PortA and PortB can be separately
defined,whib PortC is dividedintotwo portionsas
requiredby the PortA and PortB definitions.
All of
the ouput registers,includingthe statusflip-flops,
will be resetwheneverthe modeis changed.Modes
may be combinedso that theirfunctionaldefinition
can be "tailored"to almostany l/O structure.For
in Mode0 to
instance;GroupB can be programmed
monitorsimpleswitchclosingsor displaycomputational results,Group A could be programmedin
Mode1 to monitora keyboardor tapereaderon an
interrupt-driven
basis.
fofit a
t .liruI
o.OUT'(,I
TID€ TEIECTIOII
O. rrOOE0
Ot .li|ooE t
lx. x(DC Z
r|(lOE $T fLAG
| . ACTIVE
231256-6
Flgure6. llode DellnltlonFormat
The modedefinitionsand possiblemodecombinationsmayseemconfusingat firstbut aftera cursory
reviewof the completedeviceoperationa simple,
logicall/O approachwill surfqce.The designof the
82C55Ahastakeninto accountthingssuchas effivs PC
cientPGboardlayout,controlsignaldefinition
layoutand completefunctionalflexibilityto support
almostany pedpheraldevicewith no extemallogic.
Such designrepresentsthe maximumus€ of the
availablepins.
SlngleBlt Set/ResetFeature
Any of the eightbits of PortC can be Set or Reset
usinga singleOUTputinstruction.This featurerein Control-based
appliducessoftwarerequirements
cations.
rc
L-J
ooilTiot
t^r.a\
231256-5
.:^,'...!9
-
!-'--'
!
Figure5. BasicModeDefinltionsand Bus
lnterface
for Port
WhenPortC is beingusedas status/control
A or B, thesebitscanbe set or resetby usingthe Bit
Set/Resetoperationjust as if theyweredataoutput
ports.
3-128
inbr
oofftiot
82C55A
InterruptControlFunctlons
woiD
When the 82C55Ais programmedto operatein
mode1 or mode2, controlsignalsare providedthat
can be usedas intenuptrequestinputsto the CpU.
Theintenuptrequestsignals,generated
fromportC,
can be inhibitedor enabledby settingor resetting
the associatedINTEflip-flop,usingthe bit set/reset
functionof port C.
Thisfunctionallowsthe Programmer
to disallowor
allowa specificl/O deviceto intenuptthe CpUwithout affectinganyotherdevicein the intenuptstructure.
INTEflip-flopdefinition:
23126-7
(BIT-SET)--INTE
is SET-tnterruptenable
(BIT-RESE!-INTEis RESET-tntemrpt
disabte
Flgure7. Blt Set/ResetFormat
Note:
All Mask flip-flopsare automaticalty
reset during
modeselectio4anddeviceReset.
3-129
intef
82C5sA
Operatlngilodes
Mode0 (BaslcInput/Output).Thisfunctionalconfigurationprovidessimpleinput and outputoperationsfor eachof the threeports.No "handshaking"
is required,datais simplywrittento or readfrom a
specifiedport.
Mode0 BasicFunctional
Definitions:
o Two 8-bitportsandtwo 4-bitports.
o Any portcan be inputor output.
. Outputsare latched.
o Inpirtsare not latched.
o 16 ditferentlnput/Outputconfigurations
are possiblein thisMode.
iroDE0 (BAsrcINPUT)
231256-8
lrroDE0 (BASTC
OUTPUT)
231256-9
3-130
intef
82C55A
MODE0 Port Deflntilon
A
B
Da
D3
D1
D6
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
1
1
0
1
0
1
1
1
1
0
1
0
1
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
GROUPA
PORTC
PORTA
(UPPER)
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
1
1
0
1
INPUT
INPUT
0
0
0
INPUT
1
1
1
0
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
1
#
PORTB
PORTC
(LOWERI
0
OUTPUT
OUTPUT
INPUT
OUTPUT
OUTPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
OUTPUT
OUTPUT
12
13
OUTPUT
OUTPUT
INPUT
INPUT
OUTPUT
OUTPUT
14
15
INPUT
INPUT
1
2
3
4
5
6
7
8
9
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
GROUP
B
10
11
iIODE 0 Gonflgurailons
4Dc%o.o!o2DrDo
o,
oot{?RoL rYoiD at
Da
D3
O.
G(IrTiot woRo fi
07 Da 05 D.
3-131
03
D3
Dr
INPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
OUTPUT
INPUT
OUTPUT
lNPUT
int€f
82C55A
(Continued)
MODE0 Gontlguratlons
coN?RoLtoRo aa
coNrior tfoRo a
ooaf?iol roRo a6
oo{rnol
cofrlRot ifiraD G
cof{lFot woRo rro
D, Oa D3 O.
firio
0
cofltioL nono a,
oofrtior
o,
or
D!
o.
ot
o,
I
0
0
0
I
0
Dt
Do
t
3-132
ra
0
woiD afi
I
O,
02
Dr
Do
0
0
I
0
82C55A
ltoDE 0
D,
(Continued)
Dt
Or
Or
Dt
D:
Dr
col{lRoL trotDria
o,
Da Dr Or
Do
I
0t0
Dr
I
Dr
0
Or
Oo
0
OOf,rlOlwloiD|,lt
D,o.OrorDrDrDr%
DrO.DrDrOro'DrOo
ffi
Opcratlng todcr
ilODE 1 (Strobed Input/Output).This functional
provid€sa meansfor transfeningl/O
configuration
data to or from a specifi€dport in conjunctionwith
strobesor "handshaking"
signals.In mode1, portA
and Port B use the lineson PortC to generateor
acc€ptthese"handshaking"
signals.
Mode1 BasicfunctionalDefinitions:
o Two Groups(GroupA and GroupB).
o Eaghgroupcontainsone B-bitdataportand one
4-bit control/dataport.
.
Ih9 8-bitdata port can be eitherinputor output
Bothinputsand outputsare latched.
. The4-bitportis usedfor controlandstatusof the
8-bit data port.
3-133
intel
82C55A
InputControlSlgnalDeflnltlon
SE (Strole Input). A "low" on this input loads
dataintothe inputlatch.
ooiriol roio
DrDr4D.DrO2Otql
IBF (lnput Buffer Full F/F)
ttr
aE^
atf^
I.lt.'tt
A "high" on this outputindicatesthat the data has
beenloadedintothe inputlatch;in essence,an acknowledgement.
IBF is set by STBingJ beinglow
and is resetby the risingedgeof the RD input.
O. OUTrur
txti^
iD
r/o
INTR(lntenupt Requeet)
A "high" on this outputcan be usedto intenuptthe
CPU when an input deviceis requestingservice.
INTRis set by the STBis a "one", IBFis a "on€"
andINTEis a "one". lt is resetby the fallingedgeof
ffi. tris procedureallowsan input deviceto request servicefrom the CPUby simplystrobingits
dataintothe port.
INTEA
Controlledby bit set/resetof PCa.
ItrlTEB
Controlledby bit set/resetof PC2.
or D, ot Do
Illr
|lta
ilrt
23r256-13
Flguref. ilODE I Input
231256-14
Flgure9. IIODE 1 (StrobedInput)
3-134
intef
82C55A
OutputGontrolSlgnalDeflnlilon
OFr lOutpurBuftcr Fuil F/F). The6EF ouput witl
go "low" to indicatethat the CPUhas writtendata
outto the specifiedport.TheffiF fff wiil be set bv
the dsingedgeof the WF inputand resetby ffi
Inputbeinglow.
ooiattol
t oio
FR (lctnow_ledgeInput). A "low,' on this input
informsthe 82C55AthatthedatafromportA or iort
B hasbeenaccepted.In essence,a responsefrom
the peripheraldeviceindicatingthat it his received
the dataoutputby the CPU.
lilTR (lntenupt Roquest).A "high"'onthisoutput
can be usedto intenuptthe CpU whenan output
devicehas accepteddata transmittedby the CpU.
INTRis set whenAffi is a "on€", OEF-isa ,,one"
gE INTEis a "one". lt is resetby the fallingedgeof
WR.
x(Dl I GOiT]
4OrQO.DrOrOiOo
FMWFDA
ilh
EC
INTEA
Controlledby bit set/resetof pe.
INTEB
Controlledby bit set/resetof pC2.
rmt
231256-15
Flgurel0.llODE I Output
rt
flt
tx?t
fi
o|ttttrt
231256-16
Flgurcll.llODE I (SrrobedOurput)
3-135
intef
82C55A
Comblnatlons
of MODE1
PortA and PortB canbe individually
delinedas inputor outputin Mode1 to supporta widevarietyof strobed
l/O applications.
EFA
m^
cof{TRottronD
rcnrA-taTtot€otilrutl
loFT I - (stiolED Ot''n ?l
IORTA-(STROTEOOUTruTI
roRlt-(sTRoaEonruTl
231256-17
Flgure12.Comblnatlons
of iIODEI
Operatlngllodes
OutputOperatlons
MODE 2 (Strobed Bidlrectlonal Bus l/O).This
providesa meansfor comfunctionalconfiguration
municating
witha peripheral
deviceor structureon a
single8-bit bus for both transmittingand receiving
bus l/O). "Handshaking"
data(bidirectional
signals
areprovidedto maintainproperbusflowdisciplinein
a similarmannerto MODE1. Interuptgeneration
functionsare alsoavailable.
and enable/disable
ffi lOutput Bufler Full).Ths OBF outputwill go
"lof' to indicatethat the CPUhaswrittendataout
to portA.
MODE2 BasicFunctionalDefinitions:
o Usedin GroupA only.
r One8-bit,bi-directional
busport(PortA) anda 5bit controlport (PortC).
o Bothinputsand outputsare latched.
o The s-bit controlport (PortG) is usedloi control
bus port
and statuslor the 8-bit, bi-directional
(PortA).
INTE 1 (The INTE Fllp-Flop Assoclated wlth
OBF).Controlledby bit set/resetof PC6.
BldirectionalBus l/O ControlSlgnalDefinltion
INTR(lnterruptRequest).A highon thisoutputcan
be usedto interrupttheCPUfor inputor outputoperations.
EK (Acfnowledge).A "low" on this inputenables
the tri-stateoutputbutferof PortA to sendout the
data.CIherwise,
the outputbutferwillbe in the high
impedance
state.
Input Operatlons
S?E lStroUe Input). A "low" on this input loads
dataintothe inputlatch.
IBF(lnputBufterFullF/F).A "high"on thisoutput
indicatesthat data has been loadedinto the input
latch.
INTE2 (The INTEFlip-FlopAssoclatedwlth IBF).
Controlledby bit set/resetof PGa.
3-136
int€f
82C55A
coil?iot
06
o.
woRD
D'
or
tQo
l.nnT
0. OUlrur
toat a
l - lttuT
0. OUnU?
ceout BrbDE
0. I|oDE0
r . l | o O EI
231256-18
Flgure13.MODEControlWord
231256-19
Flgure14.llODE2
DAt trcr
ctu tot2ctaa
NF
ilF
tftlR
ET
3tt
IBF
'ERI'IIEiAL
3ts
to
DA' FH
tEr|'HEnat ro aacaa
It..A
oat^ Fiol
TOPIEiflTETAL
Figure15.MODE2 (Btdtrectionat)
'
NOTE:
Any sequencewnereW-[occurs beforeFffi, anglsfBlqcurs beforeFD is permissible.
(INTR: tBFo NiAS-R.
o [66o ffiy
STE.FE + OEF.FIASK
g-197
intef
82Cs5A
ModeDeflnltlonSummary
MODEO
MODE1
MODE2
IN
ouT
IN
our
PAo
PAr
PAz
PAs
PAI
PAs
PAe
PAz
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
PBo
PBr
PBz
PBg
PBa
PBs
PBs
PBz
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
PCo
PCr
PCz
PCg
PCa
PCs
PCo
PCt
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
GROUPA ONLY
<_>
<-'
MODEO
OR MODE 1
ONLY
INTRg INTRs
lBFs OEFg
tlo
vo
vo
SfEs Affie
INTBa INTBa
SfaA
vo
lBFa t/o
vo
vo
INTBa
srEA
lBFa
ffia
6EF1
ACK-CKA
O-eFa
SpeclalModeComblnaUonConsldera$ons
Thereare severalcombinations
of modespossible.
Foranycombination,
someor all of the PortC lines
are usedfor controfor status.The remainingbits are
eitherinputsor outputsas definedby a "Set Mode"
command.
Duringa readof PortC, th€ stateof all the port C
lines,exceptthe AGK-and STB lines,will be placed
on the data bus. In placeof the Atfr and ffi tine
states,flag statuswill appearon the databusin the
PCz, PC4,and PC6 bit positionsas illustratedby
Figure18.
Througha "Writ€PortC" command,onlythe PortC
pinsprogrammed
as outputsin a Mode0 groupcan
be written.No otherpinscanbe atfectedby a "Wdte
PortC" command,norcanthe intenuptenableflags
be accessed.To write to any Port C output programmedas an output in a Mode 1 group or to
changean intenuptenableflag,the "Set/Resetport
C Bit" commandmustbe used.
Witha "Set/ResetPortC Bit" command,anyportC
line programmed
as an output(includingINTR,IBF
and OBF)can be written,or an interruptenableflag
can be eitherset or reset.PortC linesproqrammed
as inputs,includingAffi and STE linei, ajsociated
with PortC are not atlectedby a "Set/Resetport C
port C
Bit" command.Writingto the conespondinq
bit positionsof the Affi and StB'tines iitn rne
"Set/Reset Port G Bit" commandwilt afiect the
GroupA qndGroupB intenuptenableflags,as illustratedin Figure18.
CurrentDrlve Capablllty
Anyoutputon PortA, B or C can sinkor source2.5
mA.Thisfeatureaflowsthe 82Cg5Ato direcilydrive
Darlingtontype drivers and high-voltagedisplays
that requiresuchsinkor sourcecunent.
3-139
intef
82C55A
MOOE2 AND MODEO I]NPUTI
MODE 2 AND MOOEO IOUTPUT}
tq
q
r+r\
tArt\
rc'
frl^
fg
dr^
?q
Fre
q
d^
tc.
37-r^
tc.
-tt!a
rq
tlF^
rq
llF^
4DrD|D.DrDrDtOo
rro
lca
tQr
tro
ti.r+\
tlr+\
MOOE 2 ANO MOOE 1 (OUTPUTI
MDDE2 AND MODE1 IINPUTI
i%
r&rt
rC'
Fr^
tct
oa-;^
tc
Fr^
t't
E^
tc.
fi^
t
ifi^
tcr
DFe
7c!
ttt^
4Or%D.O!02DrDo
r'TryxK'ril<
rqr%
ri"rq
6Fr
fcr
iD
eclfrr
lc!
|In
lrlrFr
tco
Figure16.MODEt/oCombinations
3-138
82C554
Readlng Port C Status
ln Mode 0, Port C transfersdata to or from the peripheraldevice.Whenthe 82C55Ais programmedto
lunction in Modes 1 or 2, Port C generates or accepts "hand-shaking"signalswith the peripheraldevice. Readingthe contents of Port C allows the programmer to test or verify the "status" of each peripheral device and change the program flow accordingly.
There is no special instructionto read the status information from Port C. A normal read operation of
Port G is executedto performthis function.
INPUTCONFIGURATION
D2
Ds
D1
D5
Da
D6
h
D6
tt9lttOl IBFAI INTE1| INTRAIINTEsI lBFsI INTRg
GROUPB
GROUPA
ouTPurcot{FtGuRATtoNs
D7
D5
6EFa
INTEI
D5 Da
D3
vo t/o INTRI
GROUPA
D2
D1
D9
INTEg 6EFs INTRs
GROUPB
Figure17a.MODEI StatusWordFormat
D?
D5
D5
Da
D3
D2
D1
D6
GROUPA
GROUPB
(D€finodByMode0 or Mod€1 S€l€ction)
Flgure17b.MODE2 StatusWordFormat
lnteruDt EnableFlaq
Posltlon
AlternatePort C PinSlonal(Mode)
INTEB
PC2
Affis (OutputMode1)orSTBs(lnputMode1)
INTEA2
PC4
STBa(lnputMode1 or Mode2)
INTEA1
PC6
Affia (OutoutMode1 or Mode2
Flgure18.lnterupt EnableFlagsln ilodes 1 and 2
3-140
intef
82C55A
ABSOLUTEMAXIMUMRATINGS*
Ambient
Temperature
UnderBias.. . .0"Cto + 70'C
StorageTemperature ...- 65"Cto* 150'C
SupplyVoltage
0.5to * 8.0V
OperatingVoltage
.....+ 4Vto + 7V
Voltage
onenyInput..
. .GND-2Vto * 6.5V
Voltageon anyOutput. .GND-0.5Vto V66 + 0.5V
PowerDissipation
.....1Watt
'Notice: Slrassesabove thoselisted under "Absolute MaximumRatings"maycausepermanentdamage to the device. Thisis a stressrating only and
functionaloperationof the device at these or dny
otherconditbnsabovethoseindbatedin the operationalsectionsof thisspecificationis not implied.Exposure to absolutemaximumrating conditionsfor
ertendedpeiods mayaffect devicereliability.
D.C. CHARACTERISTICS
T A = 0 ' C t o 7 0 ' C , V C C : * 5 V ! 1 O o / oG, N D : 0 V ( T n :
Symbol
Vrt
Parameter
-40oCto *85'CforExtendedTemperture)
Mln
Itlax
Unlts
Inpul Low Voltage
-0.5
0.8
V
InputHighVoltage
2.0
Vcc
v
0.4
V
lg; : 2.5 mA
V
V
lox : -2.5 mA
lgs: -100pA
TegtCondltlons
Vrn
vol
Vox
OutputHighVottage
Iu
InputLeakageCunent
t1
pA
V1X: V66 to 0V
(Note1)
loru
OutputFloatLeakageCunent
r10
pA
V1X: V66 to 0V
(Nore2)
loen
Darlington
DdveCunent
t2.5
(Note4)
mA
PortsA, B, C
Rsl: 500O
Vexl: 1.7V
lpnt
PortHoldLowLeakageCunent
+50
+300
pA
lpxx
PortHoldHighLeakageCunent
-50
-300
pA
Vggl: 1.0V
Port A only
Vggl : 3.0V
PortsA, B, C
lpxlo
PortHoldLowOverdrive
Cunent
-350
pA
Vggry: 0.8V
lpnxo
Port Hold High OverdriveGunent
+350
pA
V9g1 : 3.0V
lcc
V66SupplyCunent
10
mA
lccss
V6s SupplyCunent-Standby
10
pA
(Note3)
VCC: 5.5V
Vtru: VCCor GND
PortConditions
lt llP : Open/High
OlP : OpenOnly
WithDataBus :
High/Low
Fs : High
Reset= Low
PureInputs:
Low/High
NOTES:
1. PinsA1,
OutputLowVoltage
3.0
V6s - 0.4
eS,WH,F-D,Reset.
-.-.2.Oata
3. Ouputsopen.
4. Limitoutputcun€nl to 4.0 mA.
3-141
intet
82C55A
CAPACITANCE
TA : 25oC,VCC: GND = 0V
Parameter
Symbol
Mln
Max
Unlts
crru
InputGapacitance
10
pF
Qro
l/O Capacitance
20
pF
TestGondltlons
plns
Unmeasured
returnedto GND
fc : 1 MHz(s)
NOTE:
5. Sampled
not'100o/o
tested.
A.C. CHARACTERISTICS
TA : Ooto 70'C, VCC: +5v t10o/o,GND : 0v
TA : -40'C to *85"C for ExtendedTemperature
BUS PARATIIETEBS
READ CYCLE
Symbol
82C55A.2
Parameter
tln
ten
tnn
tnn
tno
tor
R'Dt to DataFloating
tRv
RecoveryTimebetweenFDzWF
AddressStableBeforeFE t
0
AddressHoldTimeAfterRDf
0
H-DPutseWiOtn
tar
150
DataDelayfromRD-J,
120
10
75
2@
Unlts
Test
Condltlons
ns
ns
ns
ns
ns
ns
WRITECYCLE
Symbol
82C554.2
Parameter
tln
tew
twe
AddressStableBeforeWF I,
0
AddressHoldTimeAfterWF'f
20
20
tww
tow
WFIPubewidth
100
DataSetupTimeBeforeWF f
100
two
DataHoldTimeAfterWHf
30
30
3-142
Unltr
tar
ns
ns
ns
ns
ns
ns
ns
Test
Condltlont
PortsA & B
PortC
PortsA & B
PortC
intel
82C55A
OTHERTIMINGS
Symbol
82C55A-2
Parametor
llln
twe
trn
txn
tnx
tsr
WFi: l toOutput
Peripheral
DataBeforeR'D
Peripheral
DataAfterRDAmPulseWidth
ilax
Unlts
Condltlong
350
ns
0
ns
0
ns
200
ns
100
tps
STBPutseWidth
Per.DataBeforeSffi High
20
ns
ns
tpx
Per.DataAfterSTEHigh
50
ns
tno
txo
twos
taoe
tsrg
A-ffi:0toOuput
175
ns
250
ns
WF i : l to OB F -:O
Affi:0toOF: 1
150
ns
150
ns
StE:OtolBF:1
150
ns
tnta
RD-:ltolBF:O
150
tnr
RE:Oto|NTR:0
200
tsr
tnr
twr
tnes
SfB:lto|NTB:1
150
Efi:lto|NTR:1
150
WFi:Oto|NTR:O
200
ns
ns
ns
ns
ns
ns
Affi : 1 to OutputFtoat
ResetPulseWdth
20
500
Test
see note 1
seenote2
llOTEr
1. INTRT mayoccuras earlyas WF J.
2' Pulsewidthof initialResetpulseafter poworon mustbe at l€ast50 psec. subseguentR€setputses
maybe 500 ns
minimum.
3-143
82C55A
WAVEFORMS
roDE 0 (BASICINPUT)
2312 -U
OUTPUT)
roDE 0 (BASTC
?€1256.23
3-14/.
intef
82C55A
WAVEFORMSlcontinued)
iloDE I (STROBED
tltPUT)
rtF
tltt
FD
;[#,'.lll- - -
noDE I (STROBEDOUTPUT)
3-145
intet
82C55A
WAVEFORMS(continued)
rroDE2 (BTD|RECT|ONAL)
iloto:
Anyseguence@m
lqcurp beloe Ack AND_srB_occurs
beforeffi is permissibre.
(INTF= tar . FIASK. liTE. F'D + OEF. fifIFk r fffi o ffi;
WBITETIIIING
READTIiIING
231256-28
23125,}-27
A.C.TESTINGINPUT,OUTPUTWAVEFORII
A.C.TESTINGLOADCIRCUIT
krr'
T
I
=
?312ft-25
AC. Testing Inpub Ar€ DrivenAt 2.1V Fot A logic 1 And 0.45V
For A Logic 0 Timing Measur€menbArc Made Ai 2.0V For A
LogflcI And 0.8 For A Logic 0.
q-rntf
231256-30
'Vgg1 ls Sel At VadousVoltrges DuringTesting To
Guarantee
Th€ Sp€dticaton. C1 IncludesJig Capacitance.
3-146
IntervalTimer
lntel82C54Programmable
DataSheetReprint
intel'
82Cs4
TIMER
PROGRAMMABLE
INTERVAL
CHMOS
wlth all Inteland most
I Compatlble
mlcroprocesaors
other
r HfghSpeed,"Zero WaltState"
Operatlonwlth 8 MHz8086/88and
80186/188
I HandleeInputs from DGto 8 MHz
- 10 MHzfor 82C54-2
I AYaIIabIeIn EXPRESS
- StandardTemperatureRange
- ExtendedTemperatureRange
I Three Independent16-bltcounters
I Low PowerCHMOS
-lcc : 10 mA @8 MHzCount
frequency
r CompletelyTTL Compatlble
I Six ProgrammableCounterModee
r Blnaryor BCDcountlng
I StatusRead Back Command
I AvallableIn 24-PlnDIP and 28-PlnPLCC
The Intel82C54is a high-performance,
CHMOSvereionof the industrystandard8254counter/timer
whichis
designedto solvethe timingcontrolproblemscommonin microcomputer
systemdesign.lt providesthree
independent
16-bitcounters,
eachcapableof handlingclockinputsup to 10 MHz.All modesare sottware
programmable.
The 82C54is pin compatible
withthe HMOS8254,and is a supersetol the 8253.
Six programmable
timer modesallowthe 82C54to be usedas an ev€ntcounter,elapsedtime indicator,
programmable
one-shot,and in manyotherapplications.
The 82C54is fabricatedon Intel'sadvancedCHMOSlll technologywhichprovideslow powerconsumption
withperformance
equalto or greaterthanthe equivalentHMOSproduct.The82C54is availablein 24-pinDlp
and 28-pinplasticleadedchipcanier(PLCC)packages.
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231244-1
OAIE O
Flgure1.82C5t1
BlockDlagram
oxo
arcoa
rc
vcc
Fr
A.
clx
out
all
ric
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rg
tt
ta
OATE i
12
13
out r
ctr r
291241-2
Diagramsarefor pin teleronc€only.
Packag€siz€sare not to scal€.
Flgure2.82C54Pinout
3-83
S.ptGmbcr 1989
Ordcr l{umbcn 291244}05
intet
82C54
Table1.PlnDescrlption
Symbol
PlnNumber
PLCC
Dz'Do
DIP
1-8
CLK O
9
OUTO
GATEO
10
10
12
13
2-9
Functlon
Type
)to
data bus lines,
Data:Bidirectionaltri-state
data
bus.
connectedto system
Clock0: ClockinPutof Counter0.
0.
Output0: Outputof Gounter
Counter
0.
input
0:
Gate
of
Gate
o
11
12
13
14
15
16
17
18
20-19
20
21
23-22
G
21
24
RD-
22
26
Read Control:This input is low duringGPUread
operations.
WF
23
27
Vcc
NC
24
28
WriteControl:Thisinputis lowduringCPUwrite
ooerations.
Power:+ 5Vpowersupplyconnection.
GND
OUT1
GATE 1
CLK1
GATE2
OUT2
CLK2
At, Ao
Ground:Powersupplyponnection.
14
16
17
18
o
1.
Out1:Outputof Gounter
Gate1:Gateinoutof Counter1
Clock 1: Clock input of Counter1
't9
2.
Gate2: Gateinoutof Counter
2.
Out2: Outoutof Counter
o
Clock2: Cfockinout of Counter2.
Address:Usedto selectoneof thethreeCounters
or the ControlWordRegisterfor reador write
Normallyconnectedto thesystem
operations.
addressbus.
Selects
Ar
Ao
0
0
Counter0
Counter1
1
0
0
Counter2
1
1
1
ControlWord
Reqister
ChipSelectA lowon thisinputenablesthe82G54
to respondto ffi andWFIsignals.FD andWFIare
ionoredotherwise.
1 , 1 1 ,1 5 , 2 5
No Connect
sired defay. After the desired delay, the 82C54 will
intenupt the CPU.Sottwareoverheadis minimaland
variablelength delays can easily be accommodated.
FUNCTIONAL
DESCRIPTION
General
intervaltimer/counter
The82C54is a programmable
systems.
designedfor usewith lntel microcomputer
It is a generalpurpose,multi-timing
elementthat can
be treatedas an a,?ayof llO ports in the system
software.
The 82C54solvesone of the most commonprobsystem,the generation
femsin any microcomputer
of accuratetime delaysundersoftwarecontrol.Insteadof settingup timingloopsin software,the programmerconliguresthe 82C54to matchhis requirementsand programsone of the countersfor the de-
Some ol the other counter/timer functions common
to microcomputerswhich can be implementedwith
the 82C54are:
o
o
o
.
.
o
o
o
3-84
Realtimeclock
Even counter
Digitalone-shot
Programmablerate generator
Squarewave generator
Binaryrate multiplier
Complexwaveform generator
Complex motor controller
inbf
82C54
BlockDlagram
WORDREGISTER
CONTROL
DATA BUSBUFFER
This3-state,bi-direciional,
8-bitbutferis usedto interfacelhe 82C54to the systembus (seeFigure3).
(se6Figure4) is selected
Register
TheControlWord
LogicwhenAr, Ao : 11. lf the
by the Read/Write
to the 82C54,the
CPUthendoesa writeoperation
data is storedin the ControlWordRegisterand is
interpretedas a ControlWord used to definethe
operationof the Counters.
The ControlWord Registercan only be writtento;
statusinformationis availablewith the Read-Back
Command.
Flgure3. Block DlagramShowlngDataBus
Buffer and Read/WrlteLoglc Functlons
231244-5
READ/WRITE
LOGIC
The Read/WriteLogicacc€ptsinputsfromthe system busand generatescontrolsignalsfor the other
functionalblocksof the 82C54.A1 and Ao select
oneof thethreecount€rsor the ControlWordReoister to be readtrom/writteninto.A "low" on theFD
inputtellsthe 82C54that the CPU_i_s
readingone of
the counters.A "low" on the WR input tells the
82C54that the CPUis ryUlnge[beI a ControlWord
or an initialcount.BothRD andWR are qualifiedby
eS; FD and WF are ignoredunlessthe 82C5ahai
beenselectedby holdingCS low.
Flgure4. BlockDlagramShowlngControlWord
Registerand CounterFunctlons
couNTEB O,COUNTER
1, COUNTER
2
Thesethreefunctionalblocksare identicalin operation,so onlya singleCounterwillbe described.
The
internalblockdiagramof a singlecounteris shown
in Figure5.
The Countersare fully independent.
EachCounter
mayoperatein a ditferentMode.
The GontrolWordRegisteris shownin the figure;it
is not part of the Counteritself,but its cont€ntsdeterminehowthe Counteroperates.
3-85
stor€din the CRandlatertransfenedto the CE.The
ControlLogicallowsone registerat a time to be
loadedtromthe internalbus.Both bytesare trans'
CRy and CRLare
fenedto the CE simultaneously.
ln this
clearedwhen the Gounteris programmed.
for one
way,if the Counterhas beenprogrammed
byteonlyor least
bytecounts(eithermostsigniticant
significantbyte only) the other byte will be zero.
a
Notethatthe CEcannotbe writteninto;whenever
countis written,it is writtenintothe CR.
TheControlLogicis alsoshownin the diagram.CLK
n, GATEn, andOUTn are all connectedto the outsideworldthroughthe ControlLogic.
82C54SYSTEMINTERFACE
231244-6
Flgure5.InternalBlockDlagramof a Counter
The status register,shown in the Figure,when
latched,containsthe cunentcontentsof the Control
Word Registerand status of the output and null
countflag. (Seedetailedexplanationof the ReadBackcommand.)
Theactualcounteris
CE(for"Counting
Elelabelled
ment").lt is a 16-bitpresettable
synchronous
down
counter.
The 82C54is treatedby the systemssoftwareas an
anayof peripherall/O ports;threearecountersand
the fourthis a controlr€gisterfor MODEprogramming.
Basically,
the selectinputsAo,A1connectto the As,
A1 addressbussignalsof the CPU.The CS can be
dedveddirectlyfromthe addressbus usinga linear
selectmethod.Or it canbe connectedto the output
of a decoder,suchas an Intel8205for largersystems.
OLy and OL; are two 8-bit latches.OL standsfor
"OutputLatch";the subscriptsM and L standfor
"Most significantbyte" and "Leastsignificantbyte"
respectivefy.
Both are normallyrelerredto as one
unitandcalledjust OL.Theselatchesnormally"follow" the CE, but if a suitableCounterLatch.Commandis sent to the 82C54,the latches"latch" the
presentcountuntilreadby the CPUandthenretum
to "following"the GE,Onelatchat a timeis enabled
by the counter'sControlLogicto drivethe internal
bus.This is how the 16-bitCountercommunicates
over the 8-bit intemal bus. Note that the CE itself
cannotbe read;wheneveryou readthe count,it is
the OL that is beingread.
Simitarly,there are two 8-bit registerscalledCRy
Bothare normally
and CR1(for "CountRegister").
referredto as one unit and calledjust CFl.Whena
new count is writtento the Counter,the count is
3-86
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251244-7
Flgure6.82C54SystemInterlace
82C54
DESCRIPTION
OPERATIONAL
Programmingthe 82C54
General
by writinga ControlWord
Counters
areprogrammed
andthenan initialcount.The controlwordformatis
shownin Figure7.
After power-up,the state of the 82C54 is undefined.
The Mode, count value, and output of all Counters
are undefined.
How each Counteroperatesis determinedwhen it is
programmed.Each Counter must be programmed
before it can be used. Unusedcountersneed not be
programmed.
All ControlWordsarewrittenintothe ControlWord
Register,
whichis selectedwhenA1,A0 : 11.The
ControlWorditselfspecifieswhichCounteris being
programmed.
By contrast,initialcountsarewrittenintothe Counters,not the ControlWordRegister.
The41, As inputs are used to selectthe Counterto be written
into.Theformatof the initialcountis determined
by
the ControlWord
used.
ControlWordFormat
A1,A,g:11 G:0
ffi:1
Dt
WFI:0
D5
sc1 sc0
D5
Da
Ds D2 D1
D6
RW1 RW0 M2 M 1 MO BCD
SC- SelectCounter:
M - MODE:
]t2
Ml
scl
sco
0
0
SelectGounter0
0
0
0
Mode0
0
1
SelectGounter1
0
0
1
Mode 1
1
0
SelectCounter2
X
1
0
Mode 2
1
Read-BackGommand
(See Read Operations)
x
1
1
Mode 3
1
0
0
Mode4
1
0
1
Mode5
1
RW- Read/Wrlte:
RWl RWo
0
0
MO
BCD:
(seeRead
CounterLatchCommand
Operations)
0
0
1
Read/Write
leastsignificant
byteonly.
1
0
Flead/Writemost signiticantbyte only.
1
1
Read/Write least significantbyte first,
then most significantbyte.
1
BinaryCounter16-bits
(BCD)Counter
BinaryCodedDecimal
(4 Decades)
NOTE:Don't care bits (X) snoutdbe 0 to insure
compatibilitywith future Inlel products.
Figure7. ControlWordFormat
3-87
intet
82C54
WrlteOperations
procedurelor the 82C54is very
The programming
tlexible.Onlytwo conventionsneedto be remem'
bered:
1) For each Counter,the ControlWord must be
writtenbeforethe initialcountis writton.
2) The initialcount must follow the count format
specifiedin the ControlWord (leastsignificant
byteonly,or leastsigbyteonly,mostsignificant
nificantbyteand thenmostsignificantbyte).
Since the ControlWord Registerand the three
Countershaveseparateaddresses(selectedby the
the
Ar, Aoinputs),andeachControlWord
specifies
Counterit appliesto (SC0,SC1bits),no specialinConlrolWordLSBofcountMSBof countControlWordLSBofcountMSBof countControlWordLSBofcountMSBofcount-
A1
11
00
00
11
01
01
11
10
10
Ao
Counter0
Counter0
0
Counter
Counter'l
Counterl
Counter1
Counter2
Counler2
Count€r2
ControlWordCounterWordControlWordLSBofcountLSBofcountLSBofcountMSBof countMSBof countMSBof count-
A1
11
11
11
10
01
00
00
01
10
Ao
Counter0
Counter1
Counter2
Counter2
Counterl
Counter0
Counter0
Counter1
Gounter2
structionseguenceis required.Any programming
aboveis ac'
sequencethat lollowsthe conventions
ceptable.
A new initialcountmay be writtento a Counterat
any time without atfecting the Counter's pro'
willbe atfected
grammedModein anyway.Counting
Thenewcount
as describedin the Modedefinitions.
countformat.
mustfollowthe programmed
to read/writetwo-byte
lf a Counteris programmed
counts,the followingprecautionapplies:A program
must not transfercontrolbetweenwritingthe first
andsecondbyteto anotherroutinewhichalsowrites
intothat sameCounter.Othenrise,the Counterwill
be loadedwithan incorrectcount.
ControlWordControlWordControlWordLSBof countMSBof countLSBof countMSBof countLSBof countMSBof count-
Counter2
Counter1
Counter0
Counter2
Counter
2
Counter1
Counter1
Counter0
Counter0
ControlWordControlWord
LSBof countControlWordLSBof countMSBof countLSBof countMSBof countMSBof count-
Counter1
Counter0
Counter1
Counter2
Counter0
Counter1
Counter2
Counter0
Counter2
A1
1
1
1
Ao
1
1
1
0
0
1
1
1
0
0 '1
0
0
0
0
A1
11
11
01
11
00
01
10
00
10
Ao
NOTE:
fn all four examples,all counters ere programmedto readlwite h,vo-byteclunts.
These ar6 only four of many possibl€programmings€qu€nces.
Figure8. A FewPosslbleProgrammlngSequences
ReadOperations
It is often desirableto readthe valueof a Counter
the countin progress.
Thisis easiwithoutdisturbing
ly donein the 82C54.
There are three possiblemethodsfor readingthe
counters:a simple read operation,the Counter
Latch Command, and the Read-Back Command.
Each is explainedbelow. The first method is to perform a simple read operation.To read the Counter,
which is selected with the Al, A0 inputs, the CLK
input of the selected Counter must be inhibited by
using either the GATE input or ext€rnal logic. Otherwise, the count may be in the process of changing
when it is read, giving an undefinedresult.
3-88
int€f
82C54
grammingoperationsof other Countersmay be inserted between them.
COUNTERLATCH COMMAND
The second method uses the "Counter Latch Command". Likea ControlWord,this commandis written
to the Control Word Register, which is selected
when A1, Ao : 11. Also like a ControlWord, the
SCO,SC1 bits select one of the three Counters,but
two other bits,D5 and D4, distinguishthis command
from a GontrolWord.
Another feature of the 82C54 is that reads and
writes of the same Counter may be interleaved;for
example,if the Counteris programmedfor two byte
counts,the followingsequenceis valid.
1. Read least significantbyte.
2. Write new least significantbyte.
3. Read most significantbyte.
4. Write new most significantbyte.
A l , A o : 1 1 ;G : 0 ; F - D : 1 ;W F : 0
D7
D5 Da D3 D2 D1 De
D5
sc1 sc0
0
0
X
X
X
lf a Counter is programmedto read/write two-byte
counts,the followingprecautionapplies;A program
must not transfer control between reading the first
and secondbyteto anotherroutinewhichalso reads
from that same Counter.Othenrise, an incorrect
count will be read.
X
SC1, SCO- specifycounterto be latched
scl
sco
Counter
0l0l
0l1l
0
1
1t0t
2
1
|
1
READ.BACKCOMMAND
The third method uses the Read-Backcommand.
This commandallowsthe user to check the count
value, programmedMode, and current state of the
OUT pin and Null Countflag of the selectedcounte(s).
I Read-BackCommand
D5,D4- 00 designates
GounterLatchCommand
X - don'tcare
The commandis writteninto the ControlWordRegister and has the format shown in Figure 10. The
command applies to the counters selected by setting their conespondingbits D3,D2,D1: l.
NOTE:
Don't care bits (X) should be 0 to insurecompatibility
with future Intel products.
Figure 9. Counter Latching Command Format
A 0 , A 1: 1 1
The selectedCounter'soutput latch (OL) latchesthe
count at the time the Counter Latch Command is
received.This count is held in the latch until it is read
by the CPU (or until the Counter is reprogrammed).
The count is then unlatched automaticallyand the
OL returnsto "following"the countingelement(CE).
This allows reading the contents of the Counters
"on the fly" without affecting counting in progress.
MultipleCounterLatch Gommandsmay be used to
latch more than one Counter. Each latched Counter's OL holdsits countuntilit is read.CounterLatch
Commandsdo not affect the programmedMode of
the Counterin any way.
lf a Counter is latched and then, some time later,
latchedagain before the count is read,the second
CounterLatchCommandis ignored.The count read
will be the count at the time the first Counter Latch
Commandwas issued.
With either method,the count must be read according to the programmedformat; specifically,if the
Counter is programmed for two byte counts, two
bytes must be read. The two bytes do not have to be
read one right after the other; read or write or pro-
f,$:O
FD=1
WF=0
D5:0 : Latch count of s€lectedcounter(s)
D4:0 - Latch statusof selectedcounter(s)
D3: 1 : Selectcounter2
D2: 1 : Selectcounter1
D1:1 : S€lectcountero
Do: Reservedtor futureExpansion;must be 0
Figure 10.Read-BackCommand Format
The read-backcommandmay be used to latch multiple counter output latches (OL) by setting the
COUNTbit D5:0 and selectingthe desiredcounte(s). This single commandis functionallyequivalent to several counter latch commands, one for
each counterlatched.Each counter'slatchedcount
is held until it is read (or the counter is reprogrammed).That counter is automaticallyunlatched
when read, but other countersremain latcheduntil
they are read.lf multiplecountread-backcommands
are issuedto the same counterwithoutreadingthe
3-89
intef
82C54
count,all but the first are ignored;i.e., the count
whichwill be readis the countat the timethe first
wasissued.
read-back
command
THISACTION:
A. Writeto the control
word register:hl
g.
- Writ6to the count
,"girt"r,(cR);tel
C. Newcountis loaded
intoCE(CR+ CE);
The read-backcommandmayalsobe usedto latch
statusinformationof selectedcounter(s)by setting
ffifiiS
bit D4:0. Statusmust be latchedto be
read;statusof a counteris accessedby a readfrom
that counter.
CAUSES:
Nullcount: 1
Nullcounl= 1
Nullcount=0
ltl Only the counter specifiedby the control word will
have its null count set lo 1. Null count bits of oth€r
countersare unatfected.
I2l tt me counler is programmedtor truo-bytecounts
(l€ast significantbyt€ then most significantbyte) null
count goes to 1 when the secondbyte is written.
Thecounterstatusformatis shownin Figure11.Bits
D5 throughD0 containthe counter'sprogrammed
Modeexactlyas writtenin the last ModeGontrol
Word.OUTPUTbit D7 containsthe currentstateof
the OUT pin.This allowsthe userto monitorthe
counter'soutputvia software,possiblyeliminating
somehardwarefroma system.
Flgure12.NullCountOperation
lf multiplestatuslatchoperationsof the counter(s)
are performedwithoutreadingthe status,all butthe
first are ignored;i.e.,the statusthat will be readis
the statusof the counterat the timethe first status
wasissued.
read-back
command
D5
NULL
RW1 RW0 M2 M1 MO BCD
OUTPUT
COUNT
D 71 = O u t P i n i s 1
0:OutPinis0
D6 1 : Nullcount
0 : Countavailablefor reading
Ds-Do CounterProgrammedMode (See Figure7)
Figure 11.Status Byte
NULL COUNTbit DOindicateswhen the last count
written to the counter register(CR) has been loaded
into the countingelement(CE).The exact time this
happensdependson the Modeof the counterand is
describedin the ModeDefinitions,but untilthe count
is loadedinto the countingelement(CE),it can't be
read from the counter.lf the count is latchedor read
before this time, the count value will not reflectthe
new count just written.The operationof Null Count
is shown in Figure12.
Both count and statusof the selectedcounter(s)
may be latched simultaneously
by setting both
COUNTand STATUSbits D5,D4-0. This is functionallythe sam€as issuingtwo separateread-back
commandsat once,and the abovediscussions
apply herealso.Specifically,
if multiplecountand/or
statusread-backcommands
are issuedto the same
counter(s)withoutany intervening
reads,all but the
firstareignored.
Thisis illustrated
in Figure13.
lf bothcountandstatusof a counterarelatched,the
firstreadoperationof that counterwill returnlatched
status,regardlessof whichwas latchedfirst. The
next one or two reads(dependingon whetherthe
for one or two type counts)
counteris programmed
returnlatchedcount.Subsequentreadsreturnunlatchedcount.
Command
Descrlptlon
D7 D5 D5 Da D3 D2 D1 D6
1 1 0 0 0 0 1 0 Readbackcountandstatusof
Gounter
0
1 0 0 Read back statusof Counter1
1
1 1 0 0
1
0
1
1 0 0 Readbackstatusof Counters2, 1
1 1
1
1
0
1
1
0
0
0
Readbackcountof Counter2
1
1
0
0
0
1
0
0
Readbackcountand statusof
Counter1
1
1
1
0
0
0
1
0
Readbackstatusof Counter1
Results
Countandstatuslatched
for Counter0
Statuslatchedfor Counter1
Status latchedfor Gounter
2, but not Counter1
Countlatchedfor Counter2
Countlatchedfor Counter1
butnotstatus
Command
ignored,
status
alreadylatchedfor Counter1
Figure 13.Read-BackCommand Example
3-90
intef
82C54
G
m
0
0
0
0
0
0
1
0
1
0
0
WF Ar
Ao
0
0
0
0
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
1
1
0
1
1
1
Readfrom Counter2
No-Operation(3-State)
1
0
X
X
X
X
(3-State)
No-Operation
0
1
1
X
x
No-Operation
(3-State)
1
1
WriteintoCounter0
WriteintoCounter1
WriteintoCounter2
WriteControlWord
ReadfromCounter
0
ReadfromCounter1
Thisallowsthecounting
sequence
to be synchronized by sottware.
Again,OUTdoesnotgo highuntilN
+ 1 CLKpulsesafterthe newcountof N is written.
lf an initialcountis writtenwhileGATE: 0, it will
stillbe loadedon the nextCLKpulse.WhenGATE
goeshigh,OUTwillgo highN CLKputseslater;no
CLKpulseis neededto loadtheCounter
as thishas
alreadybeendone.
Flgure14.Read/WrlteOperailonsSummary
Mode Definitions
Tha fo.llowing
are definedfor use in describingthe
operationof the 82C84.
CLKPULSE:
a risingedge,thena tallingedge,in
thatorder,of a Counter's
CLKinput.
TRIGGER:arisingedgeof a Counter's
GATEinput.
COUNTER
LOADING:
th€transferof a countfrom
the CR to the CE (referto
the "Functional Description")
I - l - l " | " I I I i I I I I I Sl : F l 5 5 l
CWr t0
L3trt
l- l" l" l- li lt l: ll lt ls I#l
CUr t0
ltl
rt
rtt -t
MODE0: INTERRUPT
ON TERMTNAL
COUNT
yod,e9 is.typicatty
usedfor eventcounting.Afterthe
ControlWordis written,OUTis initiailyloiv,and will
remainlowuntiltheCounterreacheszero.OUTthen
goeshighand remainshighuntila newcountor a
new Mode0 ControlWordis writteninto the Counter.
GATE: 1 enablescounting;GATE: 0 disables
counting.
GATEhasno etfecton OUT.
AftertheControlWordandinitialcountarewrittento
a Counter,
theinitialcountwillbe loadedon thenext
CLKpulse.ThisCLKpulsedoesnot decrement
the
count,so for an initialcountof N, OUTdoesnot go
highuntilN + 1 CLKpulsesafterthe initiatcountis
written.
lf a new countis writtento the Counter,it will be
loadedon the nextCLKpulseandcounting
willcontinuefromthe newcount.lf a two-bytecountis written,the followinghappens:
1) Writingthefirstbytedisables
counting.
OUTis set
lowimmediately
(noclockpulserequired).
2) Writingthe secondbyteallowsthe newcountto
be loadedon the nextCLKputse.
3-91
l-l-l* l- li ltl tlt lt ls l:Il
231244-8
NOTE:
The FollowingConventions
ApplyTo All Mode Timing
Diagrams:
1. Counters.are programmedfor binary (not BCD)
counting.andfor Reading/Writing
teastsilnificantb6e
(LSB)only.
2. The counter.isalwaysselected(eS ahays low).
3. CW standslor "ConrrolWord"; CW - iO meins a
controlword of '10,hex is writtento the counter.
4. LSB standsfor "Least SignificantByte" of count.
5. Numbersbelowdiagramsare counlvalues.
The lowernumberis the leastsigniticantbyte.
The upper numberis the mostlignificani byte. Since
lhe counter is-.programmedto Read/Write LSB only,
the most significantbyte cannot be read.
N standslor an undetinedcount.
Verticallines show transitionsbetweencount values.
Figure 15.Mode 0
intet
82C54
IIODE 1: HARDWARERETRIGGERABLE
ONE.SHOT
OUT will be initiallyhigh.OUTwill go low on the CLK
pulse followinga triggerto begin the one'shot pulse,
and will remain low until the Counter reaches zero.
OUT willthengo highand remainhighuntiltheCLK
pulse after the next trigger.
After writing the Control Word and initial count' the
Gounteris armed. A trigger results in loadingthe
Counterand settingOUT low on the next CLK pulse'
thus startingthe one-shotpulse.An initialcount of N
will resultin a one-shotpulseN CLK cyclesin dura'
hence OUT will
tion. The one-shotis retriggerable,
remain low for N CLK pulses after any trigger. The
one-shotpulse can be repeatedwithoutrewritingthe
same count into the counter.GATE has no etfect on
OUT.
lf a new count is written to the Counterduringa one'
shot pulse, the current one-shot is not atfected unless the Counter is retriggered. In that case, the
Counter is loaded with the new count and the one'
shot pulse continuesuntilthe new count expires.
MODE 2: RATE GENEFATOR
This Mode functionslike a divide-by-Ncounter.lt is
typiciatlyused to generatea Real Time Clock interrirpt.OUf will initiallybe high.Whenthe initialcount
has decrementedto 1, OUT goes low for one GLK
pulse. OUT then goes high again,the Counter re'
ioads the initial count and the proc€ss is repeated.
Mode 2 is periodic;the same sequenceis repeated
indefinitely.For an initialcount of N, the sequence
repeats every N CLK cYcles.
GATE = 1 enablescounting;GATE : 0 disables
counting.lf GATE goes low duringan outputpulse'
OUT is set high immediately.A triggerreloadsthe
Counterwith the initialcounton the next CLK pulse;
OUT goes low N CLK pulsesafter the trigger.Thus
the GATE input can be used to synchronizethe
Counter.
After writing a Control Word and initial count, the
Counterwilibe loadedon the next CLK pulse' OUT
goes low N CLK Pulsesafter the initialcount is writ'
ien. This allows the Counter to be synchronizedby
software also.
rfi
FF
CLf,
ct|(
OATE
ol?€
out
oul
wt
WI
cLx
clx
o^rE
CATE
out
lolololololol
1212l312It
out
I3l
L3!ri
'Wt
cLt
WT
orr€
clK
oul
G IC
l-l"l.l-ll
lo lo
1312
lo
l'l
our
l- i" I rir jx I I i I l3i#lt:i: ll I
l0l0l
l. t3 |
231244-10
NOTE:
A GATE transitionshould not occur one clock prior lo
terminalcount.
231244-9
Flgure17.Mode 2
Figure 16.Mode 1
3-92
intef
82C54
Writinga newcountwhilecountingdoesnot atfect
the cunent countingsequence.lf a triggeris receivedatterwritinga newcountbut beforethe end
of the cunentperiod,the Counterwillbe loadedwith
the newcounton the n€xtCLKpulseand counting
will continuefrom the new count. Otherwise,th6
n€w countwill b€ loadedat th€ gnd of the cunent
countingcycle.In mode2, a COUNTof 1 is illegal.
OUTwill be highfor (N + 1)/2 countsand lowfor
(N -1)/2 counts.
9r
ctr
oltt
sl
i/IODE3: SQUAREWAVEMODE
l"l"l"l"l:
Mode_3.istypicallyusedfor Baudrategeneration.
Mode3 is similarto Mode2 exceptforthe-duty
cycle
of OUT.OUTwiltinitiallybe high.Whenhatfins ini
tial counthasexpired,OUTgoeslowfor the remainder of the count.Mode3 is periodic;
the sequence
aboveis repeatedindefinitely.
An initialcountof N
resultsin a squarewave with a periodof N CLK
cycles.
FI
cll
OAtE
st
GATE: 1 enablsscounting;GATE= O disables
cou$jng.lf GATEgoeslowwniteOUt is tow,OUTis
set high jmm€diately;
no CLK pufseis required.A
tlgger reloadsthe Counterwith tne initialcounton
the next CLK pulse.Thusthe GATEinputcan be
usedto synchronize
the Counter
9t
ctr
ul:
od
After writinga ControlWord and initialcount,the
Counterwill be loadedon the n€xtCLKpulse.This
allowsthe Counterto be synchronized
by sottware
also.
l"l"l*l.l:
ol0l0t0l
.trl.lrl
291244-',t1
Figure18.itode 3
MODE4: SOFTWARE
TRtccEREDSTROBE
OUTwjll be initiallyhigh.Whenthe initialcountexpires,OUTwill go low for one GLKpulseand then
go highagain.Thecounting
sequence
is ,.triggered,,
by writingthe initialcount.
Mode3 is implemented
as follows:
Odd counts:OUTis initialtyhigh.The initiatcount
minusone (anevennumber)is loadedon oneCLK
pulseandthenis decremented
by two on succeed_
ing CLK pulses.OneCLK gulseafterthe countexpires,OUT goes low and the Counteris reloaded
with the initialcountminusone. Succeeding
CLK
pulsesdecrement
thecountby two.Whenthecount
expires,OUT goes highagainand the Counteris
reloaded
withthe initialcount
minusone.Theabove
processis repeatedindefinitely.
So for odd counts,
lololololol
lrl.l21212l
NOTE:
A GATE transitionshould not occur one clock prior to
terminalcount.
Writinga new countwhilecountingdoesnot affect
the currentcountingsequence.ti a triggerG receivedafterwritinga newcountbut befo=rE
the end
of the currenthalf-cycleof the squarewave,the
Counterwill be loadedwith the new counton the
nextGLKpulseandcountingwill continuefromthe
newcount.Othenrise,the newcountwill be loaded
at the 6nd of the cunenthaff-cycle.
Evencounts:OUTis initiallyhigh.Theinitialcountis
loadedon one CLKpulseandthenis decremented
by two on succeeding
CLKpulses.Whenthe counr
expiresOUTchangesvalueand the Counteris reloadedwith the initialcount.The aboveprocessis
repeatedindefinitety.
lrl:lit:l:l:l:l:l:l
GATE: 1 enablescounting;GATE: 0 disables
counting.
GATEhasno etfecton OUT.
Afler writinga ControtWord and initialcount,the
Counterwiltbe loadedon the nextCLKpulse.This
CLKpulsedoesnotdecrement
the couni,so for an
initialcountof N, OUT does not strobelow until
N + 1 CLKpulsesafterthe initiatcountis written.
lf a new countis writtenduringcounting,it will be
loadedon the nextCLKputseandcounti;gwillcontinuefromthe newcount.lf a two-bytecoint is written,the followinghappens:
3-93
82C54
1) Writingthe first bytehas no etlecton counting.
2) Writingthe secondbyteallowsthe newcountto
be loadedon the nextCLKPulse'
This allowsthe sequenceto be "retriggered"by
software.OUTstrobeslow N*l CLK pulsesaftar
the newcountof N is written.
m
CLf,
oat:
oul
l " I . | ' . | . | 3| I | : | 3l : : l i : l 1 6 l
Afterwritingthe ControlWordand initialcount'the
counterwilfnotbe loadeduntilthe CLKpulseaftera
trigger.This CLK pulsedoes not decrementthe
count,so for an initialcountof N' OUTdoes not
strobelow untilN+ 1 CLKpulsesattera trigger.
A triggerresultsin theCounterbeingloadedwiththe
on the next CLK pulse.The counting
initial-count
OUTwill not strobelow
sequenceis retriggerable.
for N + 1 CLKpulsesafteranytrigger.GATEhas
no etfecton OUT.
thecurrent
lf a newcountis writtenduringcounting,
will not be atfected.lf a trigger
countingseguence
occursafterthe newcountis writtenbut beforethe
currentcountexpires,the Counterwill be loaded
with the new count on the next CLK pulse and
willcontinuefromthere.
counting
WT
FT
cLt
ctx
OAYE
cAt:
out
out
olololololrrl
l.l"l.l"l3l
t
lr
l2
|
I
l0
lFFl
Ltlr2
irn
PI
ctr
CLx
ol?E
oltE
our
OUI
l"l"l,.l*l
olololo
I
t2trt2
lo lolFFl
tl
l - 1 " I r l * l * l . l 3| : l l l : l i l s l : t l
loltFl
231244-'.12
Cw. tl
Figure19.Mode4
L3a - l
lal:
I
rh
clx
MODE 5: HARDWARETRIGGEREDSTROBE
(RETRIGGERABLE)
GAIE
OUT will initiallybe high. Countingis triggeredby a
risingedge of GATE.When the initialcount has expired,OUT will go low for one GLK pulse and then
go high again.
orrt
l| r l| r
l| r
l| r
l r II oI I| o2 lr oI |I o
lrrlr:lo
0 ItFtfEt
r
I o II
3 r a
231244-13
Flgure20.Mode5
3-94
int€f
82C54
Slgnel
Statug
llodcr
Low
OrGolng
Low
0
Dsables
countinq
Rldng
Programmlng
Enables
countino
1
2
4
Whena ControlWord is writtento a Counter,all
ControlLogicis immediately
resetandOUTgoesto
a knowninitialstate;no CLKpulsesare requiredfor
this.
1) lnitiates
counting
2) Resets output
atler next
clock
GATE
'l) Disables
counting
2) Sets output
immediately
hioh
3
OperationCommonto All Modes
Hlgh
1) Disables
counUng
2) Sets output
immodietely
hish
Initiates
counting
Enables
counting
lnitiates
counting
Enables
counting
Disables
counting
The GATEinputis alwayssampledon the rising
edgeof CLK.ln Modes0, 2, g, and4 theGATEinput
is levelsensitive,
andthe logiclevelis sampledon
therisingedgeof CLK.In Modes1,2,9, and5 the
GATEinputis rising-edge
sensitive.
ln theseModes,
q rislfr9edgeof GATE(trigger)setsan edge-sensitiveflip-flopintheCounter.
Thisftip-ftop
is thensampled on the neldrisingedgeof CLK;the flip-ftopis
resetimmediately
afterit is sampled.ln this way,a
triggerwill be detectedno mater whenit occurs-a
highlogicleveldoesnot haveto be maintained
until
the nextrisingedgeof CLK.Notethat in Modes2
and3, the GATEinputis bothedge-andlevel-sensitive. ln Modes2 and3, il a CLKsourceotherthan
the systemclock is used,GATEshouldbe pulsed
immediatety
followingWFIof a newcountvalue.
Enables
counlino
5
Initiates
countinq
Flgure21.GatePlnOperailonsSummary
MODE
0
COUNTER
iilN
irAx
COUNT COUNT
1
0
1
1
2
3
2
0
0
2
0
4
I
0
New countsare loadedand Countersare decrementedon the fallingedgeof CLK.
The largeplpossibleinitiatcountis 0; this is equivafent to 216 tor binarycountingand 104 for BCD
counting.
NOTE:
0 is eguivalent
to 216lor binarycountingand 104for
BCDcounting
Flgure22.Mlnlmumand MaxlmumInlilalCounta
TheCounterdoesnot stopwhenit reacheszero.ln.
Modes0, 1,4, and5 theCounter,,wrapsaround"to
the highestcount,eitherFFFFhexfor binarycountingor 9999for BCDcounting,
andcontinueicounting.Modes2 and3 areperiodic;theCounterreloads
itself with the initialcount and continuescounting
fromthere.
3-95
intel
82C54
'Notice:Stressasabovethosalistedunder'Abso'
lute MaximumRatings"maycausepermanentdam'
age to the device. Thisis a slress rating only ancl
finctional operationof the deviceat thesaor eny
otherconditionsabovethoseindicatedin tha open'
tionalsectionsof thisspecificationis not implied.Ex'
posure to absolutemaximumrating conditionsfor
extendedperiodsmayaffect devicereliability.
ABSOLUTEMAXIMUMRATINGS*
UnderBias... . . ' .0'Cto 70'C
Temperature
Ambient
StorageTemperature .....-65oto +150'C
-0,5 to +8.0V
SupplyVoltage
+4V to +7V
Voltage
Opera:ting
-2V
to +6.5V
.GND
.
.
V6nage
dnanylnput.
Voltageon anyOutput. 'GND-O.SVto Vs6 + 0.5V
.....1Watt
PoweiDissipation
D.C.CHARACTERISTICS
Temperature)
GND:0V) Fn : -40'c tO *85"c fOrEXtended
100/o,
Fa:0.c to 7ooc,Vcc:5Vt
Vrr
Parameter
InputLowVoltage
Vrs
lnput High Voltago
Symbol
Vol
Vox
OutoutLowVoltaoe
OutputHighVoltage
Mln
-0.5
Max
0.8
Unlts
2.O
Vne * 0.5
V
V
V
V
uA
0.4
3.0
Vec - 0.4
Test Condltlone
V
lor : 2.5mA
lox = -2.5 mA
l o r += - 1 0 0 p A
Vrr.r:Vec to 0V
t2.0
t10
20
pA
Vnr r:
166
InputLoadCunent
OutPutFloatLeakageCurrent
V66 SupplyCunent
mA
GrkFreq: ,dili;rtjg:i
lccse
Vcc SupplyGunent-StandbY
10
pA
CLKFreq : P6
dS: V66.
All Inputs/DataBusV66
AllOutputsFloating
lccsgr
V66 SupplyCurrent-StandbY
150
pA
CLKFreq: 99
Inputs,
eS : Vcc.AllOther
OPen
OutPuts
t/O Pins: VGND,
InputCapacitance
l/O Capacitance
OutputCapacitance
10
20
20
pF
f": 1MHz
pF
pins
Unmeasured
returnedto GND(S)
It
lopl
Ctru
Cvo
cour
A.C.CHARACTERISTICS
(fA : 0'C to 70oC,Vcc : 5V t10o/o, GND-0V) (fR :
pF
Ven to 0.0V
-4fG to *85'C for Extended
Temperature)
BUS PARAMETERS(NOIE1)
READCYCLE
Symbof
Parameter
tnR
AddressStableBeforeRD J
Gstabte BeforeffiJ
AddressHoldTimeAfterF'D1
m PulseWidth
tRo
DataD€lavtromFD J
tln
tsn
tRl
tno
top
tRv
DataDelayfromAddress
HD t to DataFloatins
Time
Recovery
Command
82C54
ilax
llln
45
0
0
150
120
220
90
5
200
NOTE:
'1.AC timingsmeasuredat V6x : 2.0V'VOI : 0'8V'
-+.ta--'-r
3-96
92c54-2
Itlln
30
0
0
95
Max
85
185
5
165
65
Unlta
ns
ns
ns
ns
ns
ns
ns
ns
intef
82C54
A.C. CHARACTERISTICS(Continued)
WRITECYCLE
Symbol
82C54
Mln
f,lax
Parameter
tnw
AddressStableBeforeWHJ
tsw
twn
Gstaue BeforeWHt
AddressHoldTimeAfterWR-f
tww
WR PulseWidth
tow
two
tnv
DataSetupTimeBeforeWFif
DataHoldTimeAfterWR-T
Command
RecoveryTime
82C54-2
Mln
Mar
0
0
0
0
0
Unlts
0
0
ns
ns
ns
ns
ns
ns
200
165
ns
0
150
95
95
120
CLOCKAND GATE
Symbol
82C54
Parameter
Mln
tclx
tpwx
tpwl
Tp
tp
tew
tertes
tct
Too
tooe
lwc
twc
two
tcl
Clock Period
HighPulseWidth
Low PulseWidth
GlockRiseTime
ClockFallTime
Gatewidth High
Gatewidth Low
GateSetupTimeto CLK1
Gate Hold Time After CLK 1
r25
60(3)
60(3)
100
DC
50
50
0
-5
-40
25
25
ns
50.
50
40
50
50(2)
ns
ns
50(2)
150
120
55
Units
ns
ns
ns
ns
30(3)
50(3)
25
25
OutputDelayfromCLKJ
OutputDelayfromGateJ
CLK Delayfor Loading(4)
Gate Delayfor Sampling(a)
OUT Delayfrom Mode Write
CLK Set Up for Count Latch
llax
DC
82C54-2
Mln
ilax
ns
ns
ns
ns
50
260
-5
100
100
55
40
ns
ns
45
-40
240
40
ns
ns
0
NOTES:
2' ln Modes 1.and 5 triggersare sampledon each risingclock edge.A secondtriggerwithin 120 ns (70
ns for the e2cu-21
of the risingclock edge may not be detected.
3. Low'goingglitchestha'tviolatetpwx, tpwL may cause_
erors requiringcounterr€programming.
4. Exceptfor Extendedremp., see Extendedrehp. A.c. charaaeristic-sGbw.
5. Samplednot 100o/o
tested.T1 : 2fC.
6' lf CLK present Twc min then CountequalsN+2 CLK pulses,Tyy6max equalsCountN+1
9l
CLK pulse.Tyy6min to
Tyy6max, count will be either N + 'l or N + 2 CLK pulses.
7' In Modes 1 and 5' it GATE is presentwhen wriiing a new Countvalue,at Try6 min counter
will not b€ triggered,at Tyy6
max Counterwill be triggered.
8' lf CLK presentwhen writing a Counter Latch or ReadBackCommand,at Tg1 min CLK will be
rettectedin count value
latched,at T6g max CLK will not be reflectedin the count value latcheo.Writiij'a CounterLatch
or ReadBackCommand
betweenT6; min and Tyygmax will result in a tatchedcount valluewhich is + one least signiticant
bit.
EXTENDEDTEMPERATURE
TTA:
Symbol
twc
two
40'C to +85'C for ExtendedT
82C54
Parameter
Min
Max
-25
CLK Delayfor Loading
25
GateDelayfor Sampling
-25
3-97
25
82C54-2
Itlin
Max
-25
25
-25
25
Unlts
ns
ns
intet
82C54
WAVEFORMS
231244-14
BEAO
231214-15
231244-16
3-98
intet
82C54
CLOCKAND GATE
2i12{/.-17
' lrst byt€ ol clunt belngwrttlen
A.C.TESTINGINPUT,OUTPUTWAVEFORM
A.C.TESTINGLOADCIRCUIT
INPUT/OUTPUT
It
I rrtvrct
uxotr
I
Itrarll
|?3l244-1A
A.C.Testing:Inpub are ddvenat 2.4y lor a logic,.1" and O,.ISV
for.a logic "0." Timingm€asurement8
qrg mad€at 2.OVtor a loglc
"1" and 0.8Vfor a togic,.0."
3-99
I
|
* |c ! ' t r r r
I
?
Q - l5oPF
C1 lncludeallg capadtanoo
2312U-19
APPENDIX D
WARRANTY
D-2
LIMITED WARRANTY
Real Time Devices,Inc. warrantsthe hardwareand softwareproductsit manufacturesandproducesto be free
from defecs in materialsandworkmanshipfor oneyearfollowing the dateof shipmentfrom REAL TIME DEVICES. This warrantyis limited to the original purchaserof productand is not transferable.
During the oneyear waranty period,REAL TIME DEVICESwill repair or replace,atits option, any defective
productsor partsat no additionalcharge,providedthat the productis returned,shippingprepaid,to REAL TIME
DEVICES. All replacedpartsandproductsbecomethe propertyof REAL TIME DEVICES. Before returning any
product for repair, customersare required to contactthe factory for an RMA number.
THIS LIMITED WARRANTY DOESNOT EXTEND TO ANY PRODUCTSWHICH HAVE BEEN DAM.
AGED AS A RESULTOF ACCIDENT,MISUSE,ABUSE(suchas:useof incorrectinput voltages,improperor
insufficient ventilation,failure to follow the operatinginstructionsthat areprovidedby REAL TIME DEVICES,
"acts of God" or other contingenciesbeyondthe control of REAL TIME DEVICES),OR AS A RESULT OF
SERVICEOR MODIFTCATIONBYAI{YONE OTI{ER THANREAL TIME DEVICES.EXCEPTAS EXPRESSLYSET FORTH ABOVE, NO OTIIER WARRANTIES ARE DGRESSED OR IMPLIED, INCLUDING,
BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESSFOR A
PARTICULAR PURPOSE,AND REAL TIME DEVICESE)GRESSLY DISCLAIMS ALL WARRANTIES NOT
STATED IIEREIN. ALL IMPLIED WARRANTMS,INCLUDING IMPLIED WARRANTIES FOR
MECHANTABILITY AND FITNESSFOR A PARTICULAR PURPOSE,ARE LIMITED TO TTIE DURATION
OF THIS WARRANTY. IN T}IE EVENT THE PRODUCTIS NOT FREEFROM DEFECTSAS WARRANTED
ABOVE, TI{E PURCHASER'SSOLEREMEDY SHALL BE REPAIR OR REPLACEMENTAS PROVIDED
ABOVE. UNDER NO CIRCUMSTANCESWILL REAL TIME DEVICES BE LIABLE TO THE PURCHASER
OR A}.IY USER FOR AIVY DAMAGES, INCLUDING A}.IY INCIDENTAL OR CONSEQUENTIAL DAM.
AGES,EXPENSES,LOST PRORTS,LOST SAVINGS,OR OTHERDAMAGES ARISINC OUT OF TI{E USE
OR INABILTTY TO USE TIIE PRODUCT.
SOME STATESDO NOT ALLOW TTIEEXCLUSION OR LIMITATION OF INCIDENTAL OR CONSEQIJENTIAL DAMAGES FOR CONSTJMERPRODUCTS,AND SOME STATESDO NOT ALLOW LIMITA.
TIONS ON HOW LONG AN IMPLIED WARRANTY LASTS, SO TTIE ABOVE LIMITATIONS OR EXCLUSIONSMAYNOTAPPLY TO YOU.
THIS WARRANTY GIVES YOU SPECIFICLEGAL RIGI{IS, AND YOU MAY ALSO HAVE OTIIER
RIGI{TS WHICH VARY FROM STATE TO STATE.
D-3
DlO24BoardUser-Selected
Settings
Basel/OAddress:
(hex)
(decimal)